Crimson Editor (http://www.crimsoneditor.com/) is a powerful text editor with almost everything you need, and it’s free to download (http://sourceforge.net/project/showfiles.php?group_id=168261),

However the development and support has stopped with version 3.72 May 14, 2008 and renamed to Emerald Editor.

Verification

If you add three script programs to the Crimson User Tools you will be much more effective, generating testbench files, compile files and perform simulation in modelsim.

genbench.tcl

If you integrate this script into Crimson Editor you can generate all testbench files including a simple test case and settings containing all files and compilation order.

Pressing Ctrl-6 while viewing a complex design then you will get a simple testbench including settings file needed to perform a simulation in a sub directory.

The simple testbench generates clock, reset and zeros to every other input signals and perform check to every output signals. Everything will be prepared to be able to add more test cases in the simplest way to make the testbench complete.

compile.tcl

While editing a VHDL file you you can simply compile and check for syntax errors by pressing Ctrl-1. The console output window tells you about the result and if compile errors received you get the file and line number to be able to double click to reach the code causing the failure.

If you have dependencies and a settings file containing several files needed you can compile the entire design in the same way by pressing Ctrl-2. You must have a file open located in the same directory as the settings file.

sim.tcl

When you are satisfied with the design and all test cases you can perform a complete simulation just by pressing Ctrl-3. The console output window will provide you with the result. You must have a file open located in the same directory as the settings file.

If you have a test regression list in the current settings file containing other testbench directories you will perform batch simulation of every test.

If you would like to perform a simulate of the current testbench within the modelsim GUI, with wave forms and all you can do that by pressing Ctrl-4.

Build

In the same manner as for the verification you can perform build (sythesis and Place & Route) just by pressing Ctrl-7. You will get the result in the console output window. You must have a file open located in the same directory as the build settings file.

If you have a list in the current build settings file containing build variants you will perform build of every variants.

synt.tcl

If you just want to perform synthesis without Place & Route just press Ctrl-8. You must have a file open located in the same directory as the synthesis settings file.

par.tcl

If you just want to perform Place & Route without synthesis just press Ctrl-9. You must have a file open located in the same directory as the Place & Route settings file.