MAME SVN History

199869 Revisions

r40040 Wednesday 29th July, 2015 at 06:34:21 UTC by Miodrag Milanović
Cleanups and version bump

[hash]	a7800.xml cgenie_cass.xml gameking.xml gameking3.xml i7000_card.xml ibm5170_cdrom.xml msx2_flop.xml nes.xml pet_cass.xml pet_flop.xml pet_rom.xml svi318_flop.xml
[src]	version.c
[src/emu]	mconfig.h schedule.c screen.h
[src/emu/bus/c64]	c128_partner.c c128_partner.h
[src/emu/bus/cbmiec]	c1526.h vic1515.h vic1520.h
[src/emu/bus/cpc]	ddi1.c
[src/emu/bus/msx_cart]	ascii.c moonsound.c
[src/emu/cpu/hphybrid]	hphybrid.c hphybrid.h
[src/emu/cpu/m68000]	m68kcpu.c
[src/emu/cpu/rsp]	rsp.c rspcp2.c rspcp2.h vadd.h vcl.h vmudh.h vmulh.h vrcpsq.h vrsq.h
[src/emu/cpu/sh2]	sh2.c sh2.h sh2comn.c
[src/emu/cpu/sm510]	sm510.c sm510.h sm510d.c sm510op.c sm511core.c
[src/emu/cpu/ucom4]	ucom4.h ucom4op.c
[src/emu/machine]	68230pit.c 68230pit.h atapihle.c nvram.c pci.c saturn.c smpc.c stvcd.c tms6100.c wd_fdc.h
[src/emu/netlist]	nl_base.c nl_base.h nl_factory.c nl_setup.h
[src/emu/netlist/analog]	nld_opamps.c
[src/emu/netlist/devices]	net_lib.c nld_log.h nld_system.h
[src/emu/netlist/macro]	nlm_cd4xxx.c nlm_opamp.c nlm_opamp.h nlm_other.c nlm_other.h nlm_ttl74xx.c nlm_ttl74xx.h
[src/emu/netlist/plib]	palloc.h pconfig.h plists.h pstate.c
[src/emu/netlist/solver]	mat_cr.h vector_base.h
[src/emu/netlist/tools]	nl_convert.c
[src/emu/sound]	c140.c discrete.c scsp.c tms36xx.c ymf278b.c
[src/emu/video]	hd44780.h i82730.c i82730.h mb_vcu.c rgbsse.h vooddefs.h
[src/mame]	arcade.lst mess.lst
[src/mame/audio]	seibu.h
[src/mame/drivers]	aerofgt.c aleisttl.c appoooh.c arkanoid.c atarisy1.c atarisy2.c bmcpokr.c chihiro.c coolridr.c cps2.c ddenlovr.c deadang.c deco32.c destroyr.c dreamwld.c dynax.c firebeat.c galaxian.c gladiatr.c gstriker.c itech8.c mazerbla.c mcr3.c midyunit.c mmagic.c model3.c namcona1.c naomi.c naughtyb.c nbmj9195.c nycaptor.c pcktgal.c photon2.c poolshrk.c rainbow.c sbowling.c segas32.c segaybd.c silvmil.c suna8.c system1.c system16.c taitoair.c thedealr.c tnzs.c ttchamp.c turbo.c vegas.c xyonix.c
[src/mame/includes]	cclimber.h deco32.h itech8.h micro3d.h nbmj9195.h pcktgal.h taitoair.h
[src/mame/machine]	awboard.c dc.c fd1089.c m1comm.c mc8123.h pgmcrypt.c s32comm.c s32comm.h segacrp2.c segacrp2.h
[src/mame/video]	deco32.c hexion.c itech8.c namcona1.c naughtyb.c nbmj9195.c segas32.c shadfrce.c starcrus.c taitoair.c tank8.c vsystem_spr.c
[src/mess/drivers]	apple2.c casloopy.c coleco.c daruma.c force68k.c hh_sm510.c hp64k.c i7000.c icatel.c rainbow.c rambo.c rc759.c sdk80.c smc777.c tb303.c xbox.c
[src/mess/layout]	tb303.lay
[src/mess/machine]	amstrad.c
[src/tools]	nltool.c nlwav.c

trunk/hash/a7800.xml
r248551	r248552
2370	2370	</software>
2371	2371
2372	2372	<!-- XM board enhanced -->
2373		<!-- from http://atariage.com/forums/topic/204250-donkey-kong-xm-pre-order-and-demo/ -->
	2373	<!-- from http://atariage.com/forums/topic/204250-donkey-kong-xm-pre-order-and-demo/ -->
2374	2374
2375		<!-- these ones are listed as 'working in MESS' but are apparently the only images that work on real hardware too -->
2376		<software name="dkongxm">
2377		<description>Donkey Kong (PAL, Demo, XM enhanced, V1.2)</description>
2378		<year>2012</year>
2379		<publisher><homebrew></publisher>
2380		<info name="programmer" value="TEP392" />
2381		<sharedfeat name="compatibility" value="PAL"/>
2382		<part name="cart" interface="a7800_cart">
2383		<feature name="slot" value="a78_sg9" />
2384		<dataarea name="rom" size="147456">
2385		<rom name="dkxm_demo_v12_pal.bin" size="147456" crc="9f6c0600" sha1="18409eace880dda3646792f9ec050a87a3b1b382" offset="0" />
2386		</dataarea>
2387		</part>
2388		</software>
	2375	<!-- these ones are listed as 'working in MESS' but are apparently the only images that work on real hardware too -->
	2376	<software name="dkongxm">
	2377	<description>Donkey Kong (PAL, Demo, XM enhanced, V1.2)</description>
	2378	<year>2012</year>
	2379	<publisher><homebrew></publisher>
	2380	<info name="programmer" value="TEP392" />
	2381	<sharedfeat name="compatibility" value="PAL"/>
	2382	<part name="cart" interface="a7800_cart">
	2383	<feature name="slot" value="a78_sg9" />
	2384	<dataarea name="rom" size="147456">
	2385	<rom name="dkxm_demo_v12_pal.bin" size="147456" crc="9f6c0600" sha1="18409eace880dda3646792f9ec050a87a3b1b382" offset="0" />
	2386	</dataarea>
	2387	</part>
	2388	</software>
2389	2389
2390		<software name="dkongxmu" cloneof="dkongxm">
2391		<description>Donkey Kong (NTSC, Demo, XM enhanced, V1.2)</description>
2392		<year>2012</year>
2393		<publisher><homebrew></publisher>
2394		<info name="programmer" value="TEP392" />
2395		<sharedfeat name="compatibility" value="NTSC"/>
2396		<part name="cart" interface="a7800_cart">
2397		<feature name="slot" value="a78_sg9" />
2398		<dataarea name="rom" size="147456">
2399		<rom name="dkxm_demo_v12_ntsc.bin" size="147456" crc="8b06bb4b" sha1="3129cbc91dc8f223f00db5c3273a4a330320be99" offset="0" />
2400		</dataarea>
2401		</part>
2402		</software>
	2390	<software name="dkongxmu" cloneof="dkongxm">
	2391	<description>Donkey Kong (NTSC, Demo, XM enhanced, V1.2)</description>
	2392	<year>2012</year>
	2393	<publisher><homebrew></publisher>
	2394	<info name="programmer" value="TEP392" />
	2395	<sharedfeat name="compatibility" value="NTSC"/>
	2396	<part name="cart" interface="a7800_cart">
	2397	<feature name="slot" value="a78_sg9" />
	2398	<dataarea name="rom" size="147456">
	2399	<rom name="dkxm_demo_v12_ntsc.bin" size="147456" crc="8b06bb4b" sha1="3129cbc91dc8f223f00db5c3273a4a330320be99" offset="0" />
	2400	</dataarea>
	2401	</part>
	2402	</software>
2403	2403
2404		<!-- these are listed as 'with HSC emulation' and are designed for the prosystem emulator, they simulate some of the HSC features -->
2405		<!-- remove them? -->
2406
2407		<software name="dkongxmps" cloneof="dkongxm" supported="no">
2408		<description>Donkey Kong (PAL, Demo, XM enhanced, V1.2, for prosystem emulator)</description>
2409		<year>2012</year>
2410		<publisher><homebrew></publisher>
2411		<info name="programmer" value="TEP392" />
2412		<sharedfeat name="compatibility" value="PAL"/>
2413		<part name="cart" interface="a7800_cart">
2414		<feature name="slot" value="a78_sg9" />
2415		<dataarea name="rom" size="147456">
2416		<rom name="dkxm_final_demo_pal_hsc.bin" size="147456" crc="6510b674" sha1="65b723b470d287af51e9888813149c43fb11ac26" offset="0" />
2417		</dataarea>
2418		</part>
2419		</software>
	2404	<!-- these are listed as 'with HSC emulation' and are designed for the prosystem emulator, they simulate some of the HSC features -->
	2405	<!-- remove them? -->
2420	2406
2421		<software name="dkongxmups" cloneof="dkongxm" supported="no">
2422		<description>Donkey Kong (NTSC, Demo, XM enhanced, V1.2, for prosystem emulator)</description>
2423		<year>2012</year>
2424		<publisher><homebrew></publisher>
2425		<info name="programmer" value="TEP392" />
2426		<sharedfeat name="compatibility" value="NTSC"/>
2427		<part name="cart" interface="a7800_cart">
2428		<feature name="slot" value="a78_sg9" />
2429		<dataarea name="rom" size="147456">
2430		<rom name="dkxm_final_demo_ntsc_hsc.bin" size="147456" crc="2c67fea7" sha1="7825c1946e3c7492fa9bbfae33029cd68c0d1135" offset="0" />
2431		</dataarea>
2432		</part>
2433		</software>
2434
	2407	<software name="dkongxmps" cloneof="dkongxm" supported="no">
	2408	<description>Donkey Kong (PAL, Demo, XM enhanced, V1.2, for prosystem emulator)</description>
	2409	<year>2012</year>
	2410	<publisher><homebrew></publisher>
	2411	<info name="programmer" value="TEP392" />
	2412	<sharedfeat name="compatibility" value="PAL"/>
	2413	<part name="cart" interface="a7800_cart">
	2414	<feature name="slot" value="a78_sg9" />
	2415	<dataarea name="rom" size="147456">
	2416	<rom name="dkxm_final_demo_pal_hsc.bin" size="147456" crc="6510b674" sha1="65b723b470d287af51e9888813149c43fb11ac26" offset="0" />
	2417	</dataarea>
	2418	</part>
	2419	</software>
2435	2420
	2421	<software name="dkongxmups" cloneof="dkongxm" supported="no">
	2422	<description>Donkey Kong (NTSC, Demo, XM enhanced, V1.2, for prosystem emulator)</description>
	2423	<year>2012</year>
	2424	<publisher><homebrew></publisher>
	2425	<info name="programmer" value="TEP392" />
	2426	<sharedfeat name="compatibility" value="NTSC"/>
	2427	<part name="cart" interface="a7800_cart">
	2428	<feature name="slot" value="a78_sg9" />
	2429	<dataarea name="rom" size="147456">
	2430	<rom name="dkxm_final_demo_ntsc_hsc.bin" size="147456" crc="2c67fea7" sha1="7825c1946e3c7492fa9bbfae33029cd68c0d1135" offset="0" />
	2431	</dataarea>
	2432	</part>
	2433	</software>
2436	2434
2437		<!-- an older version? sound is broken, did it work on the real hardware? -->
2438		<software name="dkongxmo" cloneof="dkongxm" supported="no">
2439		<description>Donkey Kong (PAL, Demo, XM enhanced, older)</description>
2440		<year>2012</year>
2441		<publisher><homebrew></publisher>
2442		<info name="programmer" value="TEP392" />
2443		<sharedfeat name="compatibility" value="PAL"/>
2444		<part name="cart" interface="a7800_cart">
2445		<feature name="slot" value="a78_sg9" />
2446		<dataarea name="rom" size="147456">
2447		<rom name="dkxm_final_demo_pal.bin" size="147456" crc="d362712e" sha1="118c462d6698bd23c378785f80062fdd7d65ca00" offset="0" />
2448		</dataarea>
2449		</part>
2450		</software>
2451	2435
2452		<software name="dkongxmou" cloneof="dkongxm" supported="no" >
2453		<description>Donkey Kong (NTSC, Demo, XM enhanced, older)</description>
2454		<year>2012</year>
2455		<publisher><homebrew></publisher>
2456		<info name="programmer" value="TEP392" />
2457		<sharedfeat name="compatibility" value="NTSC"/>
2458		<part name="cart" interface="a7800_cart">
2459		<feature name="slot" value="a78_sg9" />
2460		<dataarea name="rom" size="147456">
2461		<rom name="dkxm_final_demo_ntsc.bin" size="147456" crc="6e170055" sha1="f4da231312da06ff9e8af5681b5013b14886b455" offset="0" />
2462		</dataarea>
2463		</part>
2464		</software>
2465
2466		<!-- this one is meant to detect PAL / NTSC and runs on an A7800 CC2 development board, without sound? based off older code? -->
2467		<software name="dkongxmcc" cloneof="dkongxm" supported="no">
2468		<description>Donkey Kong (PAL/NTSC, Demo, XM enhanced, older, for CC2 board)</description>
2469		<year>2012</year>
2470		<publisher><homebrew></publisher>
2471		<info name="programmer" value="TEP392" />
2472		<part name="cart" interface="a7800_cart">
2473		<feature name="slot" value="a78_sg9" />
2474		<dataarea name="rom" size="147456">
2475		<rom name="dkxm_final_demo.bin" size="0x20000" crc="fd503bd4" sha1="454d754a0c4603323e476d9418f343a6a1a0d017" offset="0x4000" />
2476		<rom size="0x4000" offset="0x0000" loadflag="continue" />
2477		</dataarea>
2478		</part>
2479		</software>
2480
	2436
	2437	<!-- an older version? sound is broken, did it work on the real hardware? -->
	2438	<software name="dkongxmo" cloneof="dkongxm" supported="no">
	2439	<description>Donkey Kong (PAL, Demo, XM enhanced, older)</description>
	2440	<year>2012</year>
	2441	<publisher><homebrew></publisher>
	2442	<info name="programmer" value="TEP392" />
	2443	<sharedfeat name="compatibility" value="PAL"/>
	2444	<part name="cart" interface="a7800_cart">
	2445	<feature name="slot" value="a78_sg9" />
	2446	<dataarea name="rom" size="147456">
	2447	<rom name="dkxm_final_demo_pal.bin" size="147456" crc="d362712e" sha1="118c462d6698bd23c378785f80062fdd7d65ca00" offset="0" />
	2448	</dataarea>
	2449	</part>
	2450	</software>
	2451
	2452	<software name="dkongxmou" cloneof="dkongxm" supported="no" >
	2453	<description>Donkey Kong (NTSC, Demo, XM enhanced, older)</description>
	2454	<year>2012</year>
	2455	<publisher><homebrew></publisher>
	2456	<info name="programmer" value="TEP392" />
	2457	<sharedfeat name="compatibility" value="NTSC"/>
	2458	<part name="cart" interface="a7800_cart">
	2459	<feature name="slot" value="a78_sg9" />
	2460	<dataarea name="rom" size="147456">
	2461	<rom name="dkxm_final_demo_ntsc.bin" size="147456" crc="6e170055" sha1="f4da231312da06ff9e8af5681b5013b14886b455" offset="0" />
	2462	</dataarea>
	2463	</part>
	2464	</software>
	2465
	2466	<!-- this one is meant to detect PAL / NTSC and runs on an A7800 CC2 development board, without sound? based off older code? -->
	2467	<software name="dkongxmcc" cloneof="dkongxm" supported="no">
	2468	<description>Donkey Kong (PAL/NTSC, Demo, XM enhanced, older, for CC2 board)</description>
	2469	<year>2012</year>
	2470	<publisher><homebrew></publisher>
	2471	<info name="programmer" value="TEP392" />
	2472	<part name="cart" interface="a7800_cart">
	2473	<feature name="slot" value="a78_sg9" />
	2474	<dataarea name="rom" size="147456">
	2475	<rom name="dkxm_final_demo.bin" size="0x20000" crc="fd503bd4" sha1="454d754a0c4603323e476d9418f343a6a1a0d017" offset="0x4000" />
	2476	<rom size="0x4000" offset="0x0000" loadflag="continue" />
	2477	</dataarea>
	2478	</part>
	2479	</software>
	2480
2481	2481	</softwarelist>

trunk/hash/cgenie_cass.xml
r248551	r248552
88	88	</software>
89	89
90	90	<!-- Missing: Break Out -->
91		<!-- Missing: Colour-Assembler -->
	91	<!-- Missing: Colour-Assembler -->
92	92
93	93	<software name="colcom" supported="yes">
94	94	<description>Colour Basic Compiler 3.05</description>

trunk/hash/gameking.xml
r248551	r248552
17	17	</part>
18	18	</software>
19	19
20		<software name="4in1a" supported="no">
21		<description>4 in 1 Vol. 8</description>
22		<year>200?</year>
23		<publisher>TimeTop</publisher>
24		<part name="cart" interface="gameking_cart">
25		<dataarea name="rom" size="524288">
26		<rom name="4in1_vol8.bin" size="524288" crc="6741847e" sha1="b561ca1b52e3492f86e7558722c8c8956e845bc5" offset="0x00000" />
27		</dataarea>
28		</part>
29		</software>
	20	<software name="4in1a" supported="no">
	21	<description>4 in 1 Vol. 8</description>
	22	<year>200?</year>
	23	<publisher>TimeTop</publisher>
	24	<part name="cart" interface="gameking_cart">
	25	<dataarea name="rom" size="524288">
	26	<rom name="4in1_vol8.bin" size="524288" crc="6741847e" sha1="b561ca1b52e3492f86e7558722c8c8956e845bc5" offset="0x00000" />
	27	</dataarea>
	28	</part>
	29	</software>
30	30
31		<software name="2004" supported="no">
	31	<software name="2004" supported="no">
32	32	<description>2004</description>
33	33	<year>200?</year>
34	34	<publisher>TimeTop</publisher>
r248551	r248552
238	238	</software>
239	239
240	240
241
	241
242	242	</softwarelist>

trunk/hash/gameking3.xml
r248551	r248552
5	5
6	6	<softwarelist name="gameking3" description="TimeTop GameKing 3 cartridges">
7	7
8		<software name="urgent" supported="no">
9		<description>Urgent Action</description>
10		<year>200?</year>
11		<publisher>TimeTop</publisher>
12		<part name="cart" interface="gameking_cart">
13		<dataarea name="rom" size="524288">
14		<rom name="urgenaction.gk3" size="524288" crc="dcf935f8" sha1="9c1375c622caab9e328ee66434087a18a16ea036" offset="0x00000" />
15		</dataarea>
16		</part>
17		</software>
	8	<software name="urgent" supported="no">
	9	<description>Urgent Action</description>
	10	<year>200?</year>
	11	<publisher>TimeTop</publisher>
	12	<part name="cart" interface="gameking_cart">
	13	<dataarea name="rom" size="524288">
	14	<rom name="urgenaction.gk3" size="524288" crc="dcf935f8" sha1="9c1375c622caab9e328ee66434087a18a16ea036" offset="0x00000" />
	15	</dataarea>
	16	</part>
	17	</software>
18	18
19		<software name="adventr" supported="no">
20		<description>Adventure</description>
21		<year>200?</year>
22		<publisher>TimeTop</publisher>
23		<part name="cart" interface="gameking_cart">
24		<dataarea name="rom" size="524288">
25		<rom name="adventure.gk3" size="524288" crc="70082274" sha1="83b164719b2c2d5c133ca05c9fac0102b0d88e4c" offset="0x00000" />
26		</dataarea>
27		</part>
28		</software>
29
	19	<software name="adventr" supported="no">
	20	<description>Adventure</description>
	21	<year>200?</year>
	22	<publisher>TimeTop</publisher>
	23	<part name="cart" interface="gameking_cart">
	24	<dataarea name="rom" size="524288">
	25	<rom name="adventure.gk3" size="524288" crc="70082274" sha1="83b164719b2c2d5c133ca05c9fac0102b0d88e4c" offset="0x00000" />
	26	</dataarea>
	27	</part>
	28	</software>
	29
30	30	</softwarelist>

trunk/hash/i7000_card.xml
r248551	r248552
62	62	<part name="card" interface="i7000_card">
63	63	<dataarea name="rom" size="0x6000">
64	64	<rom name="i-7107_set_vt52_v1.0_r02_25_02_86_1.rom" size="0x2000" crc="ead3f48e" sha1="ec7951591cab8e8c2cb22f7e6352c709d24b9706" offset="0x0000" />
65		<!-- the 2nd EPROM connector is unpopulated -->
	65	<!-- the 2nd EPROM connector is unpopulated -->
66	66	<rom name="i-7107_set_vt52_v1.0_r02_25_02_86_2.rom" size="0x2000" crc="da848ec0" sha1="7ed1898de94c7382c081ec3a78f60a6850daa25a" offset="0x4000" />
67		<!-- the 4th EPROM connector is unpopulated -->
	67	<!-- the 4th EPROM connector is unpopulated -->
68	68	</dataarea>
69	69	</part>
70	70	</software>

trunk/hash/ibm5170_cdrom.xml
r248551	r248552
95	95	</part>
96	96	</software>
97	97
98		<!-- Untouched image from original CD created with an ASUS DRW-1814BLT (EAC drive sample read offset reported as +6)
99		If you subtract 0x18 (4 * 6) bytes from a .wav extracted from this CHD the audio matches a rip done with EAC (verified) -->
	98	<!-- Untouched image from original CD created with an ASUS DRW-1814BLT (EAC drive sample read offset reported as +6)
	99	If you subtract 0x18 (4 * 6) bytes from a .wav extracted from this CHD the audio matches a rip done with EAC (verified) -->
100	100	<software name="kingsq6e">
101	101	<description>King's Quest VI (Windows 3.1 enhanced)</description>
102	102	<year>1993</year>
r248551	r248552
109	109	</part>
110	110	</software>
111	111
112		<!-- Untouched image from original CD created with an ASUS DRW-1814BLT (EAC drive sample read offset reported as +6)
113		If you subtract 0x18 (4 * 6) bytes from a .wav extracted from this CHD the audio matches a rip done with EAC (verified) -->
	112	<!-- Untouched image from original CD created with an ASUS DRW-1814BLT (EAC drive sample read offset reported as +6)
	113	If you subtract 0x18 (4 * 6) bytes from a .wav extracted from this CHD the audio matches a rip done with EAC (verified) -->
114	114	<software name="krondor">
115	115	<description>Betrayal at Krondor (1994 release, CDDA)</description>
116	116	<year>1994</year>
r248551	r248552
122	122	</diskarea>
123	123	</part>
124	124	</software>
125
	125
126	126	<software name="krondora" cloneof="krondor">
127	127	<description>Betrayal at Krondor (1998 release, no CDDA)</description>
128	128	<year>1998</year>
r248551	r248552
135	135	</part>
136	136	</software>
137	137
138		<!-- various Windows CDROMs
139		so far the listed discs should all be full english language retail discs, this can be expanded later -->
140
	138	<!-- various Windows CDROMs
	139	so far the listed discs should all be full english language retail discs, this can be expanded later -->
	140
141	141	<software name="win95">
142	142	<description>Windows 95 (en 4.00.950)</description>
143	143	<year>1995</year>
r248551	r248552
161	161	</diskarea>
162	162	</part>
163	163	</software>
164
	164
165	165	<software name="win95b">
166	166	<description>Windows 95 OSR2 (en 4.00.1111.osr2)</description> <!-- aka Windows 95B -->
167	167	<year>1995</year>
r248551	r248552
172	172	<disk name="win95_4.00.1111_osr2_en" sha1="e15bd9a4e2c930bd4913996a2d9d11d1567635f5" />
173	173	</diskarea>
174	174	</part>
175		</software>
176
177		<software name="win95c">
	175	</software>
	176
	177	<software name="win95c">
178	178	<description>Windows 95 OSR2.5 (en 4.03.1216.osr2.5)</description> <!-- aka Windows 95C -->
179	179	<year>1995</year>
180	180	<publisher>Microsoft</publisher>
r248551	r248552
184	184	<disk name="win95_4.03.1216_osr2_5_en" sha1="b000931531cedcbb3f9a00d13d315406cf7c2d52" />
185	185	</diskarea>
186	186	</part>
187		</software>
188
189		<software name="win98">
	187	</software>
	188
	189	<software name="win98">
190	190	<description>Windows 98 (en 4.10.1998) (Retail Full)</description> <!-- aka Windows 98 First Edition -->
191	191	<year>1998</year>
192	192	<publisher>Microsoft</publisher>
r248551	r248552
198	198	</part>
199	199	</software>
200	200
201		<software name="win98se">
	201	<software name="win98se">
202	202	<description>Windows 98 Second Edition (en 4.10.2222) (Retail Full)</description>
203	203	<year>1998</year>
204	204	<publisher>Microsoft</publisher>
r248551	r248552
210	210	</part>
211	211	</software>
212	212
213		<software name="winme">
	213	<software name="winme">
214	214	<description>Windows ME (en 4.90.3000) (Retail Full)</description> <!-- aka Millennium Edition -->
215	215	<year>1999</year>
216	216	<publisher>Microsoft</publisher>
r248551	r248552
222	222	</part>
223	223	</software>
224	224
225		<software name="win2kps4">
	225	<software name="win2kps4">
226	226	<description>Windows 2000 Professional (with Service Pack 4) (en 5.00.2195.6717)</description>
227	227	<year>1999</year>
228	228	<publisher>Microsoft</publisher>

trunk/hash/msx2_flop.xml
r248551	r248552
11175	11175	<description>The Tower? of Cabin - Cabin Panic (Jpn)</description>
11176	11176	<year>1992</year>
11177	11177	<publisher>Micro Cabin</publisher>
11178		<part name="flop1" interface="floppy_3_5">
11179		<dataarea name="flop" size="737280">
11180		<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 1 of 3).dsk" size="737280" crc="0471dbee" sha1="0e8d2b0177bd601e84c71735b4b498be2818085f" offset="0" />
11181		</dataarea>
11182		</part>
11183		<part name="flop2" interface="floppy_3_5">
11184		<dataarea name="flop" size="737280">
11185		<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 2 of 3).dsk" size="737280" crc="0d3afd17" sha1="d8cb95e558065b19f21f434a97a4a59b1892fc1a" offset="0" />
11186		</dataarea>
11187		</part>
11188		<part name="flop3" interface="floppy_3_5">
11189		<dataarea name="flop" size="737280">
11190		<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 3 of 3).dsk" size="737280" crc="9ad7d280" sha1="ed0e55d97817e9d98d563fdeb634cc6443564840" offset="0" />
11191		</dataarea>
11192		</part>
	11178	<part name="flop1" interface="floppy_3_5">
	11179	<dataarea name="flop" size="737280">
	11180	<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 1 of 3).dsk" size="737280" crc="0471dbee" sha1="0e8d2b0177bd601e84c71735b4b498be2818085f" offset="0" />
	11181	</dataarea>
	11182	</part>
	11183	<part name="flop2" interface="floppy_3_5">
	11184	<dataarea name="flop" size="737280">
	11185	<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 2 of 3).dsk" size="737280" crc="0d3afd17" sha1="d8cb95e558065b19f21f434a97a4a59b1892fc1a" offset="0" />
	11186	</dataarea>
	11187	</part>
	11188	<part name="flop3" interface="floppy_3_5">
	11189	<dataarea name="flop" size="737280">
	11190	<rom name="tower of cabin, the (1992)(micro cabin)(jp)(disk 3 of 3).dsk" size="737280" crc="9ad7d280" sha1="ed0e55d97817e9d98d563fdeb634cc6443564840" offset="0" />
	11191	</dataarea>
	11192	</part>
11193	11193	</software>
11194	11194
11195	11195	<software name="towercaba" cloneof="towercab">

trunk/hash/nes.xml
r248551	r248552
79879	79879	</dataarea>
79880	79880	</part>
79881	79881	</software>
79882
79883		<software name="mc_cb280" supported="no">
79884		<description>Coolboy RS-18 (280-in-1)</description>
79885		<year>19??</year>
79886		<publisher><unknown></publisher>
79887		<part name="cart" interface="nes_cart">
79888		<!--<feature name="slot" value="coolboy" />
79889		<feature name="pcb" value="UNL-COOLBOY" /> -->
79890		<dataarea name="prg" size="4194304">
79891		<rom name="w25q32.u5" size="4194304" crc="c9541bdf" sha1="f0ce46f18658ca5dbed881e5a80460e59820bbd0" offset="00000" />
79892		</dataarea>
79893		<!-- ?? -->
79894		<dataarea name="vram" size="131072">
79895		</dataarea>
79896		</part>
79897		</software>
79898	79882
79899		<software name="mc_samur" supported="no">
79900		<!-- a VT03 OneBus based system -->
79901		<description>Samurai (60-in-1)</description>
79902		<year>2006</year>
79903		<publisher>Team Hummer</publisher>
79904		<part name="cart" interface="nes_cart">
79905		<dataarea name="prg" size="2097152">
79906		<rom name="29lv160b.bin" size="2097152" crc="7dac8efe" sha1="ffb27ebb4299d5b9a4b976c418fcc7695200060c" offset="00000" />
79907		</dataarea>
79908		<!-- ?? -->
79909		<dataarea name="vram" size="131072">
79910		</dataarea>
79911		</part>
79912		</software>
	79883	<software name="mc_cb280" supported="no">
	79884	<description>Coolboy RS-18 (280-in-1)</description>
	79885	<year>19??</year>
	79886	<publisher><unknown></publisher>
	79887	<part name="cart" interface="nes_cart">
	79888	<!--<feature name="slot" value="coolboy" />
	79889	<feature name="pcb" value="UNL-COOLBOY" /> -->
	79890	<dataarea name="prg" size="4194304">
	79891	<rom name="w25q32.u5" size="4194304" crc="c9541bdf" sha1="f0ce46f18658ca5dbed881e5a80460e59820bbd0" offset="00000" />
	79892	</dataarea>
	79893	<!-- ?? -->
	79894	<dataarea name="vram" size="131072">
	79895	</dataarea>
	79896	</part>
	79897	</software>
79913	79898
79914		<software name="mc_sg360" supported="no">
	79899	<software name="mc_samur" supported="no">
	79900	<!-- a VT03 OneBus based system -->
	79901	<description>Samurai (60-in-1)</description>
	79902	<year>2006</year>
	79903	<publisher>Team Hummer</publisher>
	79904	<part name="cart" interface="nes_cart">
	79905	<dataarea name="prg" size="2097152">
	79906	<rom name="29lv160b.bin" size="2097152" crc="7dac8efe" sha1="ffb27ebb4299d5b9a4b976c418fcc7695200060c" offset="00000" />
	79907	</dataarea>
	79908	<!-- ?? -->
	79909	<dataarea name="vram" size="131072">
	79910	</dataarea>
	79911	</part>
	79912	</software>
	79913
	79914	<software name="mc_sg360" supported="no">
79915	79915	<description>Super Game 360-in-1</description>
79916	79916	<year>19??</year>
79917	79917	<publisher><unknown></publisher>

trunk/hash/pet_cass.xml
r248551	r248552
2635	2635	<software name="ppdm2">
2636	2636	<description>The Pet Professor Whole Numbers Fractions Decimals D-M-2</description>
2637	2637	<year>1979</year>
2638
	2638
2639	2639	<!-- pet2001n16 Side A: DEC.MULT.2-PP -->
2640	2640	<publisher>Cow Bay Computing</publisher>
2641	2641	<part name="cass" interface="cbm_cass">
r248551	r248552
2700	2700	<software name="ppds2">
2701	2701	<description>The Pet Professor Whole Numbers Fractions Decimals D-S-2</description>
2702	2702	<year>1979</year>
2703
	2703
2704	2704	<!-- pet2001n16 Side A: DEC.SUB.2-PP -->
2705	2705	<publisher>Cow Bay Computing</publisher>
2706	2706	<part name="cass" interface="cbm_cass">

trunk/hash/pet_flop.xml
r248551	r248552
168	168	<!--
169	169	VisiCalc(R) PET 2001, CBM 2001
170	170	Program Diskette and CBM 8032 32K
171		[VisiCorp logo] for 2040 and 4040
	171	[VisiCorp logo] for 2040 and 4040
172	172	One of the VisiTM programs Diskette Drives
173	173	from VisiCorp by Software Arts, Inc.
174	174
175		VisiCorpTM
176		PERSONAL SOFTWARETM
	175	VisiCorpTM
	176	PERSONAL SOFTWARETM
177	177
178	178	Program Copyright (C) 1979, 1981
179	179	Software Arts, Inc. All Rights Reserved
180		20910-5511
	180	20910-5511
181	181	-->
182	182	<part name="flop1" interface="floppy_5_25">
183	183	<dataarea name="flop" size="174848">
r248551	r248552
201	201	<!--
202	202	VisiCalc(R) PET 2001, CBM 2001
203	203	Program Diskette CBM 8032 and CBM 8096
204		[VisiCorp logo] for 8050 Diskette Drive
	204	[VisiCorp logo] for 8050 Diskette Drive
205	205	One of the VisiTM programs by Software Arts, Inc.
206	206	from VisiCorp
207	207
208		VisiCorpTM
209		PERSONAL SOFTWARETM
	208	VisiCorpTM
	209	PERSONAL SOFTWARETM
210	210
211	211	Program Copyright (C) 1979, 1982
212	212	Software Arts, Inc. All Rights Reserved
213		20910-5612
	213	20910-5612
214	214	-->
215	215	<part name="flop1" interface="floppy_5_25">
216	216	<dataarea name="flop" size="533248">
r248551	r248552
825	825	<info name="serial" value="CP2-620-580" />
826	826
827	827	<!--
828		C P / M ( R ) V e r s i o n 2 . 2
	828	C P / M ( R ) V e r s i o n 2 . 2
829	829	( C ) 1 9 7 6 - 1 9 8 0 D i g i t a l R e s e a r c h
830	830	s e r i a l # C P 2 - 6 2 0 - 5 8 0 # #
831	831	8050 format / 4040 on back (C) 1982 Madison Computer
r248551	r248552
849	849	<year>2012</year>
850	850	<publisher>Steve Gray</publisher>
851	851	<!-- These disks contain some programs typed in from the HSG manual,
852		along with new programs that were written in 2012. -->
	852	along with new programs that were written in 2012. -->
853	853
854	854	<part name="flop1" interface="floppy_5_25">
855	855	<dataarea name="flop" size="174848">

trunk/hash/pet_rom.xml
r248551	r248552
292	292	<part name="rom" interface="pet_b000_rom">
293	293	<!--
294	294	TODO: The screen fills with garbage when run like this:
295		$ mame64 pet2001n32 toolkit2
	295	$ mame64 pet2001n32 toolkit2
296	296	and started with:
297		SYS 45056
	297	SYS 45056
298	298	We need to check this and should add notes with the emulator
299	299	options required to run the various versions of Toolkit.
300	300	-->

trunk/hash/svi318_flop.xml
r248551	r248552
54	54	<dataarea name="flop" size="172032">
55	55	<rom name="cpmss.dsk" size="172032" crc="cb7f1edb" sha1="676b5752141acaba7f1056909ed75be53ff388ff" offset="0" />
56	56	</dataarea>
57		</part>
	57	</part>
58	58	</software>
59	59
60	60	<software name="cpm224ds">
r248551	r248552
65	65	<dataarea name="flop" size="346112">
66	66	<rom name="cpmds.dsk" size="346112" crc="f7323e1a" sha1="7bfd8c46f8361cb31e9f4f640448cddaad91c55b" offset="0" />
67	67	</dataarea>
68		</part>
	68	</part>
69	69	</software>
70	70
71	71	<software name="diskbas">
r248551	r248552
76	76	<dataarea name="flop" size="346112">
77	77	<rom name="diskbasic10.dsk" size="346112" crc="0744ac56" sha1="eef7d033263d1cc2703d019bf062b1a02b641570" offset="0" />
78	78	</dataarea>
79		</part>
	79	</part>
80	80	</software>
81
	81
82	82	<software name="zcpr3">
83	83	<description>Z-CPR3</description>
84	84	<year>1985?</year>
r248551	r248552
87	87	<dataarea name="flop" size="172032">
88	88	<rom name="zcpr3.dsk" size="172032" crc="a6ea5b81" sha1="c08a6743e713fe8f3b8b694cd92fc70680fc6f66" offset="0" />
89	89	</dataarea>
90		</part>
	90	</part>
91	91	</software>
92	92
93	93	</softwarelist>

trunk/src/emu/bus/c64/c128_partner.c
r248551	r248552
11	11	PCB Layout
12	12	----------
13	13
14		\|---------------\|
15		\|LS74 SW CN\|
16		\|LS09 LS273\|
17		\|LS139 RAM \|
18		\|LS133 \|
19		\| LS240 \|
20		\|LS33 ROM \|
21		\|LS09 \|
22		\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|
	14	\|---------------\|
	15	\|LS74 SW CN\|
	16	\|LS09 LS273\|
	17	\|LS139 RAM \|
	18	\|LS133 \|
	19	\| LS240 \|
	20	\|LS33 ROM \|
	21	\|LS09 \|
	22	\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|
23	23
24	24	ROM - Toshiba TMM24128AP 16Kx8 EPROM (blank label)
25	25	RAM - Sony CXK5864PN-15L 8Kx8 SRAM

trunk/src/emu/bus/c64/c128_partner.h
r248551	r248552
24	24	// ======================> partner128_t
25	25
26	26	class partner128_t : public device_t,
27		public device_c64_expansion_card_interface,
28		public device_vcs_control_port_interface
	27	public device_c64_expansion_card_interface,
	28	public device_vcs_control_port_interface
29	29	{
30	30	public:
31	31	// construction/destruction

trunk/src/emu/bus/cbmiec/c1526.h
r248551	r248552
40	40	// ======================> c1526_t
41	41
42	42	class c1526_t : public c1526_base_t,
43		public device_cbm_iec_interface
	43	public device_cbm_iec_interface
44	44	{
45	45	public:
46	46	// construction/destruction
r248551	r248552
62	62	// ======================> c4023_t
63	63
64	64	class c4023_t : public c1526_base_t,
65		public device_ieee488_interface
	65	public device_ieee488_interface
66	66	{
67	67	public:
68	68	// construction/destruction

trunk/src/emu/bus/cbmiec/vic1515.h
r248551	r248552
24	24	// ======================> vic1515_t
25	25
26	26	class vic1515_t : public device_t,
27		public device_cbm_iec_interface
	27	public device_cbm_iec_interface
28	28	{
29	29	public:
30	30	// construction/destruction

trunk/src/emu/bus/cbmiec/vic1520.h
r248551	r248552
24	24	// ======================> vic1520_t
25	25
26	26	class vic1520_t : public device_t,
27		public device_cbm_iec_interface
	27	public device_cbm_iec_interface
28	28	{
29	29	public:
30	30	// construction/destruction

trunk/src/emu/bus/cpc/ddi1.c
r248551	r248552
125	125	READ8_MEMBER(cpc_ddi1_device::fdc_r)
126	126	{
127	127	UINT8 data = 0xff;
128
	128
129	129	switch(offset)
130	130	{
131	131	case 0x00:
r248551	r248552
137	137	}
138	138	return data;
139	139	}
140

trunk/src/emu/bus/msx_cart/ascii.c
r248551	r248552
533	533	break;
534	534	}
535	535	}
536

trunk/src/emu/bus/msx_cart/moonsound.c
r248551	r248552
41	41	MCFG_YMF278B_IRQ_HANDLER(WRITELINE(msx_cart_moonsound,irq_w))
42	42	MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
43	43	MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
44		MCFG_SOUND_ROUTE(2, "lspeaker", 0.40)
45		MCFG_SOUND_ROUTE(3, "rspeaker", 0.40)
46		MCFG_SOUND_ROUTE(4, "lspeaker", 0.40)
47		MCFG_SOUND_ROUTE(5, "rspeaker", 0.40)
	44	MCFG_SOUND_ROUTE(2, "lspeaker", 0.40)
	45	MCFG_SOUND_ROUTE(3, "rspeaker", 0.40)
	46	MCFG_SOUND_ROUTE(4, "lspeaker", 0.40)
	47	MCFG_SOUND_ROUTE(5, "rspeaker", 0.40)
48	48	MACHINE_CONFIG_END
49	49
50	50
r248551	r248552
124	124	LOG(("moonsound: read 0xc0\n"));
125	125	return 0x00;
126	126	}
127

trunk/src/emu/cpu/hphybrid/hphybrid.c
r248551	r248552
6	6	#include "hphybrid.h"
7	7
8	8	enum {
9		HPHYBRID_A,
10		HPHYBRID_B,
11		HPHYBRID_C,
12		HPHYBRID_D,
13		HPHYBRID_P,
14		HPHYBRID_R,
15		HPHYBRID_IV,
16		HPHYBRID_PA,
17		HPHYBRID_DMAPA,
18		HPHYBRID_DMAMA,
19		HPHYBRID_DMAC,
20		HPHYBRID_I
	9	HPHYBRID_A,
	10	HPHYBRID_B,
	11	HPHYBRID_C,
	12	HPHYBRID_D,
	13	HPHYBRID_P,
	14	HPHYBRID_R,
	15	HPHYBRID_IV,
	16	HPHYBRID_PA,
	17	HPHYBRID_DMAPA,
	18	HPHYBRID_DMAMA,
	19	HPHYBRID_DMAC,
	20	HPHYBRID_I
21	21	};
22	22
23	23	#define BIT_MASK(n) (1U << (n))
r248551	r248552
51	51
52	52	WRITE_LINE_MEMBER(hp_hybrid_cpu_device::dmar_w)
53	53	{
54		if (state) {
55		BIT_SET(m_flags , HPHYBRID_DMAR_BIT);
56		} else {
57		BIT_CLR(m_flags , HPHYBRID_DMAR_BIT);
58		}
	54	if (state) {
	55	BIT_SET(m_flags , HPHYBRID_DMAR_BIT);
	56	} else {
	57	BIT_CLR(m_flags , HPHYBRID_DMAR_BIT);
	58	}
59	59	}
60	60
61	61	hp_hybrid_cpu_device::hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname)
62	62	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
63		m_program_config("program", ENDIANNESS_BIG, 16, 16, -1),
64		m_io_config("io", ENDIANNESS_BIG, 16, 6, -1)
	63	m_program_config("program", ENDIANNESS_BIG, 16, 16, -1),
	64	m_io_config("io", ENDIANNESS_BIG, 16, 6, -1)
65	65	{
66	66	}
67	67
68	68	void hp_hybrid_cpu_device::device_start()
69	69	{
70		m_reg_A = 0;
71		m_reg_B = 0;
72		m_reg_P = HP_RESET_ADDR;
73		m_reg_R = 0;
74		m_reg_C = 0;
75		m_reg_D = 0;
76		m_reg_IV = 0;
77		m_reg_PA[ 0 ] = 0;
78		m_reg_PA[ 1 ] = 0;
79		m_reg_PA[ 2 ] = 0;
80		m_flags = 0;
81		m_dmapa = 0;
82		m_dmama = 0;
83		m_dmac = 0;
84		m_reg_I = 0;
	70	m_reg_A = 0;
	71	m_reg_B = 0;
	72	m_reg_P = HP_RESET_ADDR;
	73	m_reg_R = 0;
	74	m_reg_C = 0;
	75	m_reg_D = 0;
	76	m_reg_IV = 0;
	77	m_reg_PA[ 0 ] = 0;
	78	m_reg_PA[ 1 ] = 0;
	79	m_reg_PA[ 2 ] = 0;
	80	m_flags = 0;
	81	m_dmapa = 0;
	82	m_dmama = 0;
	83	m_dmac = 0;
	84	m_reg_I = 0;
85	85
86		{
87		state_add(HPHYBRID_A, "A", m_reg_A);
88		state_add(HPHYBRID_B, "B", m_reg_B);
89		state_add(HPHYBRID_C, "C", m_reg_C);
90		state_add(HPHYBRID_D, "D", m_reg_D);
91		state_add(HPHYBRID_P, "P", m_reg_P);
92		state_add(STATE_GENPC, "GENPC", m_reg_P).noshow();
93		state_add(HPHYBRID_R, "R", m_reg_R);
94		state_add(STATE_GENSP, "GENSP", m_reg_R).noshow();
95		state_add(HPHYBRID_IV, "IV", m_reg_IV);
96		state_add(HPHYBRID_PA, "PA", m_reg_PA[ 0 ]);
97		state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%9s");
98		state_add(HPHYBRID_DMAPA , "DMAPA" , m_dmapa).noshow();
99		state_add(HPHYBRID_DMAMA , "DMAMA" , m_dmama).noshow();
100		state_add(HPHYBRID_DMAC , "DMAC" , m_dmac).noshow();
101		state_add(HPHYBRID_I , "I" , m_reg_I).noshow();
102		}
	86	{
	87	state_add(HPHYBRID_A, "A", m_reg_A);
	88	state_add(HPHYBRID_B, "B", m_reg_B);
	89	state_add(HPHYBRID_C, "C", m_reg_C);
	90	state_add(HPHYBRID_D, "D", m_reg_D);
	91	state_add(HPHYBRID_P, "P", m_reg_P);
	92	state_add(STATE_GENPC, "GENPC", m_reg_P).noshow();
	93	state_add(HPHYBRID_R, "R", m_reg_R);
	94	state_add(STATE_GENSP, "GENSP", m_reg_R).noshow();
	95	state_add(HPHYBRID_IV, "IV", m_reg_IV);
	96	state_add(HPHYBRID_PA, "PA", m_reg_PA[ 0 ]);
	97	state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%9s");
	98	state_add(HPHYBRID_DMAPA , "DMAPA" , m_dmapa).noshow();
	99	state_add(HPHYBRID_DMAMA , "DMAMA" , m_dmama).noshow();
	100	state_add(HPHYBRID_DMAC , "DMAC" , m_dmac).noshow();
	101	state_add(HPHYBRID_I , "I" , m_reg_I).noshow();
	102	}
103	103
104		m_program = &space(AS_PROGRAM);
105		m_direct = &m_program->direct();
106		m_io = &space(AS_IO);
	104	m_program = &space(AS_PROGRAM);
	105	m_direct = &m_program->direct();
	106	m_io = &space(AS_IO);
107	107
108		save_item(NAME(m_reg_A));
109		save_item(NAME(m_reg_B));
110		save_item(NAME(m_reg_C));
111		save_item(NAME(m_reg_D));
112		save_item(NAME(m_reg_P));
113		save_item(NAME(m_reg_R));
114		save_item(NAME(m_reg_IV));
115		save_item(NAME(m_reg_PA[0]));
116		save_item(NAME(m_reg_PA[1]));
117		save_item(NAME(m_reg_PA[2]));
118		save_item(NAME(m_flags));
119		save_item(NAME(m_dmapa));
120		save_item(NAME(m_dmama));
121		save_item(NAME(m_dmac));
122		save_item(NAME(m_reg_I));
	108	save_item(NAME(m_reg_A));
	109	save_item(NAME(m_reg_B));
	110	save_item(NAME(m_reg_C));
	111	save_item(NAME(m_reg_D));
	112	save_item(NAME(m_reg_P));
	113	save_item(NAME(m_reg_R));
	114	save_item(NAME(m_reg_IV));
	115	save_item(NAME(m_reg_PA[0]));
	116	save_item(NAME(m_reg_PA[1]));
	117	save_item(NAME(m_reg_PA[2]));
	118	save_item(NAME(m_flags));
	119	save_item(NAME(m_dmapa));
	120	save_item(NAME(m_dmama));
	121	save_item(NAME(m_dmac));
	122	save_item(NAME(m_reg_I));
123	123
124		m_icountptr = &m_icount;
	124	m_icountptr = &m_icount;
125	125	}
126	126
127	127	void hp_hybrid_cpu_device::device_reset()
128	128	{
129		m_reg_P = HP_RESET_ADDR;
130		m_reg_I = RM(m_reg_P);
131		m_flags = 0;
	129	m_reg_P = HP_RESET_ADDR;
	130	m_reg_I = RM(m_reg_P);
	131	m_flags = 0;
132	132	}
133	133
134	134	void hp_hybrid_cpu_device::execute_run()
135	135	{
136		do {
137		if (BIT(m_flags , HPHYBRID_DMAEN_BIT) && BIT(m_flags , HPHYBRID_DMAR_BIT)) {
138		handle_dma();
139		} else {
140		debugger_instruction_hook(this, m_reg_P);
	136	do {
	137	if (BIT(m_flags , HPHYBRID_DMAEN_BIT) && BIT(m_flags , HPHYBRID_DMAR_BIT)) {
	138	handle_dma();
	139	} else {
	140	debugger_instruction_hook(this, m_reg_P);
141	141
142		// Check for interrupts
143		check_for_interrupts();
	142	// Check for interrupts
	143	check_for_interrupts();
144	144
145		m_reg_I = execute_one(m_reg_I);
146		}
147		} while (m_icount > 0);
	145	m_reg_I = execute_one(m_reg_I);
	146	}
	147	} while (m_icount > 0);
148	148	}
149	149
150	150	void hp_hybrid_cpu_device::execute_set_input(int inputnum, int state)
151	151	{
152		if (inputnum < HPHYBRID_INT_LVLS) {
153		if (state) {
154		BIT_SET(m_flags , HPHYBRID_IRH_BIT + inputnum);
155		} else {
156		BIT_CLR(m_flags , HPHYBRID_IRH_BIT + inputnum);
157		}
158		}
	152	if (inputnum < HPHYBRID_INT_LVLS) {
	153	if (state) {
	154	BIT_SET(m_flags , HPHYBRID_IRH_BIT + inputnum);
	155	} else {
	156	BIT_CLR(m_flags , HPHYBRID_IRH_BIT + inputnum);
	157	}
	158	}
159	159	}
160	160
161	161	/**
r248551	r248552
167	167	*/
168	168	UINT16 hp_hybrid_cpu_device::execute_one(UINT16 opcode)
169	169	{
170		if ((opcode & 0x7fe0) == 0x7000) {
171		// EXE
172		m_icount -= 8;
173		return RM(opcode & 0x1f);
174		} else {
175		m_reg_P = execute_one_sub(opcode);
176		return RM(m_reg_P);
177		}
	170	if ((opcode & 0x7fe0) == 0x7000) {
	171	// EXE
	172	m_icount -= 8;
	173	return RM(opcode & 0x1f);
	174	} else {
	175	m_reg_P = execute_one_sub(opcode);
	176	return RM(m_reg_P);
	177	}
178	178	}
179	179
180	180	/**
r248551	r248552
186	186	*/
187	187	UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode)
188	188	{
189		UINT16 ea;
190		UINT16 tmp;
	189	UINT16 ea;
	190	UINT16 tmp;
191	191
192		switch (opcode & 0x7800) {
193		case 0x0000:
194		// LDA
195		m_icount -= 13;
196		m_reg_A = RM(get_ea(opcode));
197		break;
	192	switch (opcode & 0x7800) {
	193	case 0x0000:
	194	// LDA
	195	m_icount -= 13;
	196	m_reg_A = RM(get_ea(opcode));
	197	break;
198	198
199		case 0x0800:
200		// LDB
201		m_icount -= 13;
202		m_reg_B = RM(get_ea(opcode));
203		break;
	199	case 0x0800:
	200	// LDB
	201	m_icount -= 13;
	202	m_reg_B = RM(get_ea(opcode));
	203	break;
204	204
205		case 0x1000:
206		// CPA
207		m_icount -= 16;
208		if (m_reg_A != RM(get_ea(opcode))) {
209		// Skip next instruction
210		return m_reg_P + 2;
211		}
212		break;
	205	case 0x1000:
	206	// CPA
	207	m_icount -= 16;
	208	if (m_reg_A != RM(get_ea(opcode))) {
	209	// Skip next instruction
	210	return m_reg_P + 2;
	211	}
	212	break;
213	213
214		case 0x1800:
215		// CPB
216		m_icount -= 16;
217		if (m_reg_B != RM(get_ea(opcode))) {
218		// Skip next instruction
219		return m_reg_P + 2;
220		}
221		break;
	214	case 0x1800:
	215	// CPB
	216	m_icount -= 16;
	217	if (m_reg_B != RM(get_ea(opcode))) {
	218	// Skip next instruction
	219	return m_reg_P + 2;
	220	}
	221	break;
222	222
223		case 0x2000:
224		// ADA
225		m_icount -= 13;
226		do_add(m_reg_A , RM(get_ea(opcode)));
227		break;
	223	case 0x2000:
	224	// ADA
	225	m_icount -= 13;
	226	do_add(m_reg_A , RM(get_ea(opcode)));
	227	break;
228	228
229		case 0x2800:
230		// ADB
231		m_icount -= 13;
232		do_add(m_reg_B , RM(get_ea(opcode)));
233		break;
	229	case 0x2800:
	230	// ADB
	231	m_icount -= 13;
	232	do_add(m_reg_B , RM(get_ea(opcode)));
	233	break;
234	234
235		case 0x3000:
236		// STA
237		m_icount -= 13;
238		WM(get_ea(opcode) , m_reg_A);
239		break;
	235	case 0x3000:
	236	// STA
	237	m_icount -= 13;
	238	WM(get_ea(opcode) , m_reg_A);
	239	break;
240	240
241		case 0x3800:
242		// STB
243		m_icount -= 13;
244		WM(get_ea(opcode) , m_reg_B);
245		break;
	241	case 0x3800:
	242	// STB
	243	m_icount -= 13;
	244	WM(get_ea(opcode) , m_reg_B);
	245	break;
246	246
247		case 0x4000:
248		// JSM
249		m_icount -= 17;
250		WM(++m_reg_R , m_reg_P);
251		return get_ea(opcode);
	247	case 0x4000:
	248	// JSM
	249	m_icount -= 17;
	250	WM(++m_reg_R , m_reg_P);
	251	return get_ea(opcode);
252	252
253		case 0x4800:
254		// ISZ
255		m_icount -= 19;
256		ea = get_ea(opcode);
257		tmp = RM(ea) + 1;
258		WM(ea , tmp);
259		if (tmp == 0) {
260		// Skip next instruction
261		return m_reg_P + 2;
262		}
263		break;
	253	case 0x4800:
	254	// ISZ
	255	m_icount -= 19;
	256	ea = get_ea(opcode);
	257	tmp = RM(ea) + 1;
	258	WM(ea , tmp);
	259	if (tmp == 0) {
	260	// Skip next instruction
	261	return m_reg_P + 2;
	262	}
	263	break;
264	264
265		case 0x5000:
266		// AND
267		m_icount -= 13;
268		m_reg_A &= RM(get_ea(opcode));
269		break;
	265	case 0x5000:
	266	// AND
	267	m_icount -= 13;
	268	m_reg_A &= RM(get_ea(opcode));
	269	break;
270	270
271		case 0x5800:
272		// DSZ
273		m_icount -= 19;
274		ea = get_ea(opcode);
275		tmp = RM(ea) - 1;
276		WM(ea , tmp);
277		if (tmp == 0) {
278		// Skip next instruction
279		return m_reg_P + 2;
280		}
281		break;
	271	case 0x5800:
	272	// DSZ
	273	m_icount -= 19;
	274	ea = get_ea(opcode);
	275	tmp = RM(ea) - 1;
	276	WM(ea , tmp);
	277	if (tmp == 0) {
	278	// Skip next instruction
	279	return m_reg_P + 2;
	280	}
	281	break;
282	282
283		case 0x6000:
284		// IOR
285		m_icount -= 13;
286		m_reg_A \|= RM(get_ea(opcode));
287		break;
	283	case 0x6000:
	284	// IOR
	285	m_icount -= 13;
	286	m_reg_A \|= RM(get_ea(opcode));
	287	break;
288	288
289		case 0x6800:
290		// JMP
291		m_icount -= 8;
292		return get_ea(opcode);
	289	case 0x6800:
	290	// JMP
	291	m_icount -= 8;
	292	return get_ea(opcode);
293	293
294		default:
295		switch (opcode & 0xfec0) {
296		case 0x7400:
297		// RZA
298		// SZA
299		m_icount -= 14;
300		return get_skip_addr(opcode , m_reg_A == 0);
	294	default:
	295	switch (opcode & 0xfec0) {
	296	case 0x7400:
	297	// RZA
	298	// SZA
	299	m_icount -= 14;
	300	return get_skip_addr(opcode , m_reg_A == 0);
301	301
302		case 0x7440:
303		// RIA
304		// SIA
305		m_icount -= 14;
306		return get_skip_addr(opcode , m_reg_A++ == 0);
	302	case 0x7440:
	303	// RIA
	304	// SIA
	305	m_icount -= 14;
	306	return get_skip_addr(opcode , m_reg_A++ == 0);
307	307
308		case 0x7480:
309		// SFS
310		// SFC
311		m_icount -= 14;
312		// TODO: read flag bit
313		return get_skip_addr(opcode , true);
	308	case 0x7480:
	309	// SFS
	310	// SFC
	311	m_icount -= 14;
	312	// TODO: read flag bit
	313	return get_skip_addr(opcode , true);
314	314
315		case 0x7C00:
316		// RZB
317		// SZB
318		m_icount -= 14;
319		return get_skip_addr(opcode , m_reg_B == 0);
	315	case 0x7C00:
	316	// RZB
	317	// SZB
	318	m_icount -= 14;
	319	return get_skip_addr(opcode , m_reg_B == 0);
320	320
321		case 0x7C40:
322		// RIB
323		// SIB
324		m_icount -= 14;
325		return get_skip_addr(opcode , m_reg_B++ == 0);
	321	case 0x7C40:
	322	// RIB
	323	// SIB
	324	m_icount -= 14;
	325	return get_skip_addr(opcode , m_reg_B++ == 0);
326	326
327		case 0x7c80:
328		// SSS
329		// SSC
330		m_icount -= 14;
331		// TODO: read status bit
332		return get_skip_addr(opcode , true);
	327	case 0x7c80:
	328	// SSS
	329	// SSC
	330	m_icount -= 14;
	331	// TODO: read status bit
	332	return get_skip_addr(opcode , true);
333	333
334		case 0x7cc0:
335		// SHS
336		// SHC
337		m_icount -= 14;
338		return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_HALT_BIT));
	334	case 0x7cc0:
	335	// SHS
	336	// SHC
	337	m_icount -= 14;
	338	return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_HALT_BIT));
339	339
340		default:
341		switch (opcode & 0xfe00) {
342		case 0x7600:
343		// SLA
344		// RLA
345		m_icount -= 14;
346		return get_skip_addr_sc(opcode , m_reg_A , 0);
	340	default:
	341	switch (opcode & 0xfe00) {
	342	case 0x7600:
	343	// SLA
	344	// RLA
	345	m_icount -= 14;
	346	return get_skip_addr_sc(opcode , m_reg_A , 0);
347	347
348		case 0x7e00:
349		// SLB
350		// RLB
351		m_icount -= 14;
352		return get_skip_addr_sc(opcode , m_reg_B , 0);
	348	case 0x7e00:
	349	// SLB
	350	// RLB
	351	m_icount -= 14;
	352	return get_skip_addr_sc(opcode , m_reg_B , 0);
353	353
354		case 0xf400:
355		// SAP
356		// SAM
357		m_icount -= 14;
358		return get_skip_addr_sc(opcode , m_reg_A , 15);
	354	case 0xf400:
	355	// SAP
	356	// SAM
	357	m_icount -= 14;
	358	return get_skip_addr_sc(opcode , m_reg_A , 15);
359	359
360		case 0xf600:
361		// SOC
362		// SOS
363		m_icount -= 14;
364		return get_skip_addr_sc(opcode , m_flags , HPHYBRID_O_BIT);
	360	case 0xf600:
	361	// SOC
	362	// SOS
	363	m_icount -= 14;
	364	return get_skip_addr_sc(opcode , m_flags , HPHYBRID_O_BIT);
365	365
366		case 0xfc00:
367		// SBP
368		// SBM
369		m_icount -= 14;
370		return get_skip_addr_sc(opcode , m_reg_B , 15);
	366	case 0xfc00:
	367	// SBP
	368	// SBM
	369	m_icount -= 14;
	370	return get_skip_addr_sc(opcode , m_reg_B , 15);
371	371
372		case 0xfe00:
373		// SEC
374		// SES
375		m_icount -= 14;
376		return get_skip_addr_sc(opcode , m_flags , HPHYBRID_C_BIT);
	372	case 0xfe00:
	373	// SEC
	374	// SES
	375	m_icount -= 14;
	376	return get_skip_addr_sc(opcode , m_flags , HPHYBRID_C_BIT);
377	377
378		default:
379		switch (opcode & 0xfff0) {
380		case 0xf100:
381		// AAR
382		tmp = (opcode & 0xf) + 1;
383		m_icount -= (9 + tmp);
384		// A shift by 16 positions is equivalent to a shift by 15
385		tmp = tmp > 15 ? 15 : tmp;
386		m_reg_A = ((m_reg_A ^ 0x8000) >> tmp) - (0x8000 >> tmp);
387		break;
	378	default:
	379	switch (opcode & 0xfff0) {
	380	case 0xf100:
	381	// AAR
	382	tmp = (opcode & 0xf) + 1;
	383	m_icount -= (9 + tmp);
	384	// A shift by 16 positions is equivalent to a shift by 15
	385	tmp = tmp > 15 ? 15 : tmp;
	386	m_reg_A = ((m_reg_A ^ 0x8000) >> tmp) - (0x8000 >> tmp);
	387	break;
388	388
389		case 0xf900:
390		// ABR
391		tmp = (opcode & 0xf) + 1;
392		m_icount -= (9 + tmp);
393		tmp = tmp > 15 ? 15 : tmp;
394		m_reg_B = ((m_reg_B ^ 0x8000) >> tmp) - (0x8000 >> tmp);
395		break;
	389	case 0xf900:
	390	// ABR
	391	tmp = (opcode & 0xf) + 1;
	392	m_icount -= (9 + tmp);
	393	tmp = tmp > 15 ? 15 : tmp;
	394	m_reg_B = ((m_reg_B ^ 0x8000) >> tmp) - (0x8000 >> tmp);
	395	break;
396	396
397		case 0xf140:
398		// SAR
399		tmp = (opcode & 0xf) + 1;
400		m_icount -= (9 + tmp);
401		m_reg_A >>= tmp;
402		break;
	397	case 0xf140:
	398	// SAR
	399	tmp = (opcode & 0xf) + 1;
	400	m_icount -= (9 + tmp);
	401	m_reg_A >>= tmp;
	402	break;
403	403
404		case 0xf940:
405		// SBR
406		tmp = (opcode & 0xf) + 1;
407		m_icount -= (9 + tmp);
408		m_reg_B >>= tmp;
409		break;
	404	case 0xf940:
	405	// SBR
	406	tmp = (opcode & 0xf) + 1;
	407	m_icount -= (9 + tmp);
	408	m_reg_B >>= tmp;
	409	break;
410	410
411		case 0xf180:
412		// SAL
413		tmp = (opcode & 0xf) + 1;
414		m_icount -= (9 + tmp);
415		m_reg_A <<= tmp;
416		break;
	411	case 0xf180:
	412	// SAL
	413	tmp = (opcode & 0xf) + 1;
	414	m_icount -= (9 + tmp);
	415	m_reg_A <<= tmp;
	416	break;
417	417
418		case 0xf980:
419		// SBL
420		tmp = (opcode & 0xf) + 1;
421		m_icount -= (9 + tmp);
422		m_reg_B <<= tmp;
423		break;
	418	case 0xf980:
	419	// SBL
	420	tmp = (opcode & 0xf) + 1;
	421	m_icount -= (9 + tmp);
	422	m_reg_B <<= tmp;
	423	break;
424	424
425		case 0xf1c0:
426		// RAR
427		tmp = (opcode & 0xf) + 1;
428		m_icount -= (9 + tmp);
429		m_reg_A = (m_reg_A >> tmp) \| (m_reg_A << (16 - tmp));
430		break;
	425	case 0xf1c0:
	426	// RAR
	427	tmp = (opcode & 0xf) + 1;
	428	m_icount -= (9 + tmp);
	429	m_reg_A = (m_reg_A >> tmp) \| (m_reg_A << (16 - tmp));
	430	break;
431	431
432		case 0xf9c0:
433		// RBR
434		tmp = (opcode & 0xf) + 1;
435		m_icount -= (9 + tmp);
436		m_reg_B = (m_reg_B >> tmp) \| (m_reg_B << (16 - tmp));
437		break;
	432	case 0xf9c0:
	433	// RBR
	434	tmp = (opcode & 0xf) + 1;
	435	m_icount -= (9 + tmp);
	436	m_reg_B = (m_reg_B >> tmp) \| (m_reg_B << (16 - tmp));
	437	break;
438	438
439		default:
440		if ((opcode & 0xf760) == 0x7160) {
441		// Place/withdraw instructions
442		m_icount -= 23;
443		do_pw(opcode);
444		} else if ((opcode & 0xff80) == 0xf080) {
445		// RET
446		m_icount -= 16;
447		if (BIT(opcode , 6)) {
448		// Pop PA stack
449		if (BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) {
450		BIT_CLR(m_flags , HPHYBRID_IRH_SVC_BIT);
451		memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
452		} else if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
453		BIT_CLR(m_flags , HPHYBRID_IRL_SVC_BIT);
454		memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
455		}
456		}
457		tmp = RM(m_reg_R--) + (opcode & 0x1f);
458		return BIT(opcode , 5) ? tmp - 0x20 : tmp;
459		} else {
460		switch (opcode) {
461		case 0x7100:
462		// SDO
463		m_icount -= 12;
464		BIT_SET(m_flags , HPHYBRID_DMADIR_BIT);
465		break;
	439	default:
	440	if ((opcode & 0xf760) == 0x7160) {
	441	// Place/withdraw instructions
	442	m_icount -= 23;
	443	do_pw(opcode);
	444	} else if ((opcode & 0xff80) == 0xf080) {
	445	// RET
	446	m_icount -= 16;
	447	if (BIT(opcode , 6)) {
	448	// Pop PA stack
	449	if (BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) {
	450	BIT_CLR(m_flags , HPHYBRID_IRH_SVC_BIT);
	451	memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
	452	} else if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
	453	BIT_CLR(m_flags , HPHYBRID_IRL_SVC_BIT);
	454	memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
	455	}
	456	}
	457	tmp = RM(m_reg_R--) + (opcode & 0x1f);
	458	return BIT(opcode , 5) ? tmp - 0x20 : tmp;
	459	} else {
	460	switch (opcode) {
	461	case 0x7100:
	462	// SDO
	463	m_icount -= 12;
	464	BIT_SET(m_flags , HPHYBRID_DMADIR_BIT);
	465	break;
466	466
467		case 0x7108:
468		// SDI
469		m_icount -= 12;
470		BIT_CLR(m_flags , HPHYBRID_DMADIR_BIT);
471		break;
	467	case 0x7108:
	468	// SDI
	469	m_icount -= 12;
	470	BIT_CLR(m_flags , HPHYBRID_DMADIR_BIT);
	471	break;
472	472
473		case 0x7110:
474		// EIR
475		m_icount -= 12;
476		BIT_SET(m_flags , HPHYBRID_INTEN_BIT);
477		break;
	473	case 0x7110:
	474	// EIR
	475	m_icount -= 12;
	476	BIT_SET(m_flags , HPHYBRID_INTEN_BIT);
	477	break;
478	478
479		case 0x7118:
480		// DIR
481		m_icount -= 12;
482		BIT_CLR(m_flags , HPHYBRID_INTEN_BIT);
483		break;
	479	case 0x7118:
	480	// DIR
	481	m_icount -= 12;
	482	BIT_CLR(m_flags , HPHYBRID_INTEN_BIT);
	483	break;
484	484
485		case 0x7120:
486		// DMA
487		m_icount -= 12;
488		BIT_SET(m_flags , HPHYBRID_DMAEN_BIT);
489		break;
	485	case 0x7120:
	486	// DMA
	487	m_icount -= 12;
	488	BIT_SET(m_flags , HPHYBRID_DMAEN_BIT);
	489	break;
490	490
491		case 0x7138:
492		// DDR
493		m_icount -= 12;
494		BIT_CLR(m_flags , HPHYBRID_DMAEN_BIT);
495		break;
	491	case 0x7138:
	492	// DDR
	493	m_icount -= 12;
	494	BIT_CLR(m_flags , HPHYBRID_DMAEN_BIT);
	495	break;
496	496
497		case 0x7140:
498		// DBL
499		m_icount -= 12;
500		BIT_CLR(m_flags , HPHYBRID_DB_BIT);
501		break;
	497	case 0x7140:
	498	// DBL
	499	m_icount -= 12;
	500	BIT_CLR(m_flags , HPHYBRID_DB_BIT);
	501	break;
502	502
503		case 0x7148:
504		// CBL
505		m_icount -= 12;
506		BIT_CLR(m_flags , HPHYBRID_CB_BIT);
507		break;
	503	case 0x7148:
	504	// CBL
	505	m_icount -= 12;
	506	BIT_CLR(m_flags , HPHYBRID_CB_BIT);
	507	break;
508	508
509		case 0x7150:
510		// DBU
511		m_icount -= 12;
512		BIT_SET(m_flags , HPHYBRID_DB_BIT);
513		break;
	509	case 0x7150:
	510	// DBU
	511	m_icount -= 12;
	512	BIT_SET(m_flags , HPHYBRID_DB_BIT);
	513	break;
514	514
515		case 0x7158:
516		// CBU
517		m_icount -= 12;
518		BIT_SET(m_flags , HPHYBRID_CB_BIT);
519		break;
	515	case 0x7158:
	516	// CBU
	517	m_icount -= 12;
	518	BIT_SET(m_flags , HPHYBRID_CB_BIT);
	519	break;
520	520
521		case 0xf020:
522		// TCA
523		m_icount -= 9;
524		m_reg_A = ~m_reg_A;
525		do_add(m_reg_A , 1);
526		break;
	521	case 0xf020:
	522	// TCA
	523	m_icount -= 9;
	524	m_reg_A = ~m_reg_A;
	525	do_add(m_reg_A , 1);
	526	break;
527	527
528		case 0xf060:
529		// CMA
530		m_icount -= 9;
531		m_reg_A = ~m_reg_A;
532		break;
	528	case 0xf060:
	529	// CMA
	530	m_icount -= 9;
	531	m_reg_A = ~m_reg_A;
	532	break;
533	533
534		case 0xf820:
535		// TCB
536		m_icount -= 9;
537		m_reg_B = ~m_reg_B;
538		do_add(m_reg_B , 1);
539		break;
	534	case 0xf820:
	535	// TCB
	536	m_icount -= 9;
	537	m_reg_B = ~m_reg_B;
	538	do_add(m_reg_B , 1);
	539	break;
540	540
541		case 0xf860:
542		// CMB
543		m_icount -= 9;
544		m_reg_B = ~m_reg_B;
545		break;
	541	case 0xf860:
	542	// CMB
	543	m_icount -= 9;
	544	m_reg_B = ~m_reg_B;
	545	break;
546	546
547		default:
548		// Unrecognized instructions: NOP
549		// Execution time is fictional
550		m_icount -= 6;
551		}
552		}
553		}
554		}
555		}
556		}
	547	default:
	548	// Unrecognized instructions: NOP
	549	// Execution time is fictional
	550	m_icount -= 6;
	551	}
	552	}
	553	}
	554	}
	555	}
	556	}
557	557
558		return m_reg_P + 1;
	558	return m_reg_P + 1;
559	559	}
560	560
561	561	void hp_hybrid_cpu_device::state_string_export(const device_state_entry &entry, std::string &str)
562	562	{
563		if (entry.index() == STATE_GENFLAGS) {
564		strprintf(str, "%s %s %c %c",
565		BIT(m_flags , HPHYBRID_DB_BIT) ? "Db":"..",
566		BIT(m_flags , HPHYBRID_CB_BIT) ? "Cb":"..",
567		BIT(m_flags , HPHYBRID_O_BIT) ? 'O':'.',
568		BIT(m_flags , HPHYBRID_C_BIT) ? 'E':'.');
569		}
	563	if (entry.index() == STATE_GENFLAGS) {
	564	strprintf(str, "%s %s %c %c",
	565	BIT(m_flags , HPHYBRID_DB_BIT) ? "Db":"..",
	566	BIT(m_flags , HPHYBRID_CB_BIT) ? "Cb":"..",
	567	BIT(m_flags , HPHYBRID_O_BIT) ? 'O':'.',
	568	BIT(m_flags , HPHYBRID_C_BIT) ? 'E':'.');
	569	}
570	570	}
571	571
572	572	offs_t hp_hybrid_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
573	573	{
574		extern CPU_DISASSEMBLE(hp_hybrid);
575		return CPU_DISASSEMBLE_NAME(hp_hybrid)(this, buffer, pc, oprom, opram, options);
	574	extern CPU_DISASSEMBLE(hp_hybrid);
	575	return CPU_DISASSEMBLE_NAME(hp_hybrid)(this, buffer, pc, oprom, opram, options);
576	576	}
577	577
578	578	UINT16 hp_hybrid_cpu_device::get_ea(UINT16 opcode)
579	579	{
580		UINT16 base;
581		UINT16 off;
	580	UINT16 base;
	581	UINT16 off;
582	582
583		if (BIT(opcode , 10)) {
584		// Current page
585		base = m_reg_P;
586		} else {
587		// Base page
588		base = 0;
589		}
	583	if (BIT(opcode , 10)) {
	584	// Current page
	585	base = m_reg_P;
	586	} else {
	587	// Base page
	588	base = 0;
	589	}
590	590
591		off = opcode & 0x3ff;
592		if (off & 0x200) {
593		off -= 0x400;
594		}
	591	off = opcode & 0x3ff;
	592	if (off & 0x200) {
	593	off -= 0x400;
	594	}
595	595
596		base += off;
	596	base += off;
597	597
598		if (BIT(opcode , 15)) {
599		// Indirect addressing
600		m_icount -= 6;
601		return RM(base);
602		} else {
603		// Direct addressing
604		return base;
605		}
	598	if (BIT(opcode , 15)) {
	599	// Indirect addressing
	600	m_icount -= 6;
	601	return RM(base);
	602	} else {
	603	// Direct addressing
	604	return base;
	605	}
606	606	}
607	607
608	608	void hp_hybrid_cpu_device::do_add(UINT16& addend1 , UINT16 addend2)
609	609	{
610		UINT32 tmp = addend1 + addend2;
	610	UINT32 tmp = addend1 + addend2;
611	611
612		if (BIT(tmp , 16)) {
613		// Carry
614		BIT_SET(m_flags , HPHYBRID_C_BIT);
615		}
	612	if (BIT(tmp , 16)) {
	613	// Carry
	614	BIT_SET(m_flags , HPHYBRID_C_BIT);
	615	}
616	616
617		if (BIT((tmp ^ addend1) & (tmp ^ addend2) , 15)) {
618		// Overflow
619		BIT_SET(m_flags , HPHYBRID_O_BIT);
620		}
	617	if (BIT((tmp ^ addend1) & (tmp ^ addend2) , 15)) {
	618	// Overflow
	619	BIT_SET(m_flags , HPHYBRID_O_BIT);
	620	}
621	621
622		addend1 = (UINT16)tmp;
	622	addend1 = (UINT16)tmp;
623	623	}
624	624
625	625	UINT16 hp_hybrid_cpu_device::get_skip_addr(UINT16 opcode , bool condition) const
626	626	{
627		bool skip_val = BIT(opcode , 8) != 0;
	627	bool skip_val = BIT(opcode , 8) != 0;
628	628
629		if (condition == skip_val) {
630		UINT16 off = opcode & 0x1f;
	629	if (condition == skip_val) {
	630	UINT16 off = opcode & 0x1f;
631	631
632		if (BIT(opcode , 5)) {
633		off -= 0x20;
634		}
635		return m_reg_P + off;
636		} else {
637		return m_reg_P + 1;
638		}
	632	if (BIT(opcode , 5)) {
	633	off -= 0x20;
	634	}
	635	return m_reg_P + off;
	636	} else {
	637	return m_reg_P + 1;
	638	}
639	639	}
640	640
641	641	UINT16 hp_hybrid_cpu_device::get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n)
642	642	{
643		bool val = BIT(v , n);
	643	bool val = BIT(v , n);
644	644
645		if (BIT(opcode , 7)) {
646		if (BIT(opcode , 6)) {
647		BIT_SET(v , n);
648		} else {
649		BIT_CLR(v , n);
650		}
651		}
	645	if (BIT(opcode , 7)) {
	646	if (BIT(opcode , 6)) {
	647	BIT_SET(v , n);
	648	} else {
	649	BIT_CLR(v , n);
	650	}
	651	}
652	652
653		return get_skip_addr(opcode , val);
	653	return get_skip_addr(opcode , val);
654	654	}
655	655
656	656	void hp_hybrid_cpu_device::do_pw(UINT16 opcode)
657	657	{
658		UINT16 tmp;
659		UINT16 reg_addr = opcode & 7;
660		UINT16 *ptr_reg;
661		UINT16 b_mask;
	658	UINT16 tmp;
	659	UINT16 reg_addr = opcode & 7;
	660	UINT16 *ptr_reg;
	661	UINT16 b_mask;
662	662
663		if (BIT(opcode , 3)) {
664		ptr_reg = &m_reg_D;
665		b_mask = BIT_MASK(HPHYBRID_DB_BIT);
666		} else {
667		ptr_reg = &m_reg_C;
668		b_mask = BIT_MASK(HPHYBRID_CB_BIT);
669		}
	663	if (BIT(opcode , 3)) {
	664	ptr_reg = &m_reg_D;
	665	b_mask = BIT_MASK(HPHYBRID_DB_BIT);
	666	} else {
	667	ptr_reg = &m_reg_C;
	668	b_mask = BIT_MASK(HPHYBRID_CB_BIT);
	669	}
670	670
671		if (BIT(opcode , 4)) {
672		// Withdraw
673		if (BIT(opcode , 11)) {
674		// Byte
675		UINT32 tmp_addr = (UINT32)(*ptr_reg);
676		if (m_flags & b_mask) {
677		tmp_addr \|= 0x10000;
678		}
679		tmp = RM((UINT16)(tmp_addr >> 1));
680		if (BIT(tmp_addr , 0)) {
681		tmp &= 0xff;
682		} else {
683		tmp >>= 8;
684		}
685		} else {
686		// Word
687		tmp = RM(*ptr_reg);
688		}
689		WM(reg_addr , tmp);
	671	if (BIT(opcode , 4)) {
	672	// Withdraw
	673	if (BIT(opcode , 11)) {
	674	// Byte
	675	UINT32 tmp_addr = (UINT32)(*ptr_reg);
	676	if (m_flags & b_mask) {
	677	tmp_addr \|= 0x10000;
	678	}
	679	tmp = RM((UINT16)(tmp_addr >> 1));
	680	if (BIT(tmp_addr , 0)) {
	681	tmp &= 0xff;
	682	} else {
	683	tmp >>= 8;
	684	}
	685	} else {
	686	// Word
	687	tmp = RM(*ptr_reg);
	688	}
	689	WM(reg_addr , tmp);
690	690
691		if (BIT(opcode , 7)) {
692		// Post-decrement
693		if ((*ptr_reg)-- == 0) {
694		m_flags ^= b_mask;
695		}
696		} else {
697		// Post-increment
698		if (++(*ptr_reg) == 0) {
699		m_flags ^= b_mask;
700		}
701		}
702		} else {
703		// Place
704		if (BIT(opcode , 7)) {
705		// Pre-decrement
706		if ((*ptr_reg)-- == 0) {
707		m_flags ^= b_mask;
708		}
709		} else {
710		// Pre-increment
711		if (++(*ptr_reg) == 0) {
712		m_flags ^= b_mask;
713		}
714		}
715		tmp = RM(reg_addr);
716		if (BIT(opcode , 11)) {
717		// Byte
718		UINT32 tmp_addr = (UINT32)(*ptr_reg);
719		if (m_flags & b_mask) {
720		tmp_addr \|= 0x10000;
721		}
722		WMB(tmp_addr , (UINT8)tmp);
723		} else {
724		// Word
725		WM(*ptr_reg , tmp);
726		}
727		}
	691	if (BIT(opcode , 7)) {
	692	// Post-decrement
	693	if ((*ptr_reg)-- == 0) {
	694	m_flags ^= b_mask;
	695	}
	696	} else {
	697	// Post-increment
	698	if (++(*ptr_reg) == 0) {
	699	m_flags ^= b_mask;
	700	}
	701	}
	702	} else {
	703	// Place
	704	if (BIT(opcode , 7)) {
	705	// Pre-decrement
	706	if ((*ptr_reg)-- == 0) {
	707	m_flags ^= b_mask;
	708	}
	709	} else {
	710	// Pre-increment
	711	if (++(*ptr_reg) == 0) {
	712	m_flags ^= b_mask;
	713	}
	714	}
	715	tmp = RM(reg_addr);
	716	if (BIT(opcode , 11)) {
	717	// Byte
	718	UINT32 tmp_addr = (UINT32)(*ptr_reg);
	719	if (m_flags & b_mask) {
	720	tmp_addr \|= 0x10000;
	721	}
	722	WMB(tmp_addr , (UINT8)tmp);
	723	} else {
	724	// Word
	725	WM(*ptr_reg , tmp);
	726	}
	727	}
728	728	}
729	729
730	730	void hp_hybrid_cpu_device::check_for_interrupts(void)
731	731	{
732		if (!BIT(m_flags , HPHYBRID_INTEN_BIT) \|\| BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) {
733		return;
734		}
	732	if (!BIT(m_flags , HPHYBRID_INTEN_BIT) \|\| BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) {
	733	return;
	734	}
735	735
736		int irqline;
	736	int irqline;
737	737
738		if (BIT(m_flags , HPHYBRID_IRH_BIT)) {
739		// Service high-level interrupt
740		BIT_SET(m_flags , HPHYBRID_IRH_SVC_BIT);
741		irqline = HPHYBRID_IRH;
742		} else if (BIT(m_flags , HPHYBRID_IRL_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
743		// Service low-level interrupt
744		BIT_SET(m_flags , HPHYBRID_IRL_SVC_BIT);
745		irqline = HPHYBRID_IRL;
746		} else {
747		return;
748		}
	738	if (BIT(m_flags , HPHYBRID_IRH_BIT)) {
	739	// Service high-level interrupt
	740	BIT_SET(m_flags , HPHYBRID_IRH_SVC_BIT);
	741	irqline = HPHYBRID_IRH;
	742	} else if (BIT(m_flags , HPHYBRID_IRL_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
	743	// Service low-level interrupt
	744	BIT_SET(m_flags , HPHYBRID_IRL_SVC_BIT);
	745	irqline = HPHYBRID_IRL;
	746	} else {
	747	return;
	748	}
749	749
750		// Get interrupt vector in low byte
751		UINT8 vector = (UINT8)standard_irq_callback(irqline);
752		UINT8 new_PA;
	750	// Get interrupt vector in low byte
	751	UINT8 vector = (UINT8)standard_irq_callback(irqline);
	752	UINT8 new_PA;
753	753
754		// Get highest numbered 1
755		// Don't know what happens if vector is 0, here we assume bit 7 = 1
756		if (vector == 0) {
757		new_PA = 7;
758		} else {
759		for (new_PA = 7; new_PA && !BIT(vector , 7); new_PA--, vector <<= 1) {
760		}
761		}
762		if (irqline == HPHYBRID_IRH) {
763		BIT_SET(new_PA , 3);
764		}
	754	// Get highest numbered 1
	755	// Don't know what happens if vector is 0, here we assume bit 7 = 1
	756	if (vector == 0) {
	757	new_PA = 7;
	758	} else {
	759	for (new_PA = 7; new_PA && !BIT(vector , 7); new_PA--, vector <<= 1) {
	760	}
	761	}
	762	if (irqline == HPHYBRID_IRH) {
	763	BIT_SET(new_PA , 3);
	764	}
765	765
766		// Push PA stack
767		memmove(&m_reg_PA[ 1 ] , &m_reg_PA[ 0 ] , HPHYBRID_INT_LVLS);
	766	// Push PA stack
	767	memmove(&m_reg_PA[ 1 ] , &m_reg_PA[ 0 ] , HPHYBRID_INT_LVLS);
768	768
769		CURRENT_PA = new_PA;
	769	CURRENT_PA = new_PA;
770	770
771		// Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence
772		// lasts for 32 cycles (6 are already accounted for in get_ea for one indirection)
773		m_icount -= 26;
	771	// Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence
	772	// lasts for 32 cycles (6 are already accounted for in get_ea for one indirection)
	773	m_icount -= 26;
774	774
775		// Do a double-indirect JSM IV,I instruction
776		WM(++m_reg_R , m_reg_P);
777		m_reg_P = RM(get_ea(0xc008));
778		m_reg_I = RM(m_reg_P);
	775	// Do a double-indirect JSM IV,I instruction
	776	WM(++m_reg_R , m_reg_P);
	777	m_reg_P = RM(get_ea(0xc008));
	778	m_reg_I = RM(m_reg_P);
779	779	}
780	780
781	781	void hp_hybrid_cpu_device::handle_dma(void)
782	782	{
783		// Patent hints at the fact that terminal count is detected by bit 15 of dmac being 1 after decrementing
784		bool tc = BIT(--m_dmac , 15) != 0;
785		UINT16 tmp;
	783	// Patent hints at the fact that terminal count is detected by bit 15 of dmac being 1 after decrementing
	784	bool tc = BIT(--m_dmac , 15) != 0;
	785	UINT16 tmp;
786	786
787		if (BIT(m_flags , HPHYBRID_DMADIR_BIT)) {
788		// "Outward" DMA: memory -> peripheral
789		tmp = RM(m_dmama++);
790		WIO(m_dmapa , tc ? 2 : 0 , tmp);
791		m_icount -= 10;
792		} else {
793		// "Inward" DMA: peripheral -> memory
794		tmp = RIO(m_dmapa , tc ? 2 : 0);
795		WM(m_dmama++ , tmp);
796		m_icount -= 9;
797		}
	787	if (BIT(m_flags , HPHYBRID_DMADIR_BIT)) {
	788	// "Outward" DMA: memory -> peripheral
	789	tmp = RM(m_dmama++);
	790	WIO(m_dmapa , tc ? 2 : 0 , tmp);
	791	m_icount -= 10;
	792	} else {
	793	// "Inward" DMA: peripheral -> memory
	794	tmp = RIO(m_dmapa , tc ? 2 : 0);
	795	WM(m_dmama++ , tmp);
	796	m_icount -= 9;
	797	}
798	798
799		// This is the one of the biggest question marks: is the DMA automatically disabled on TC?
800		// Here we assume it is. After all it would make no difference because there is no way
801		// to read the DMA enable flag back, so each time the DMA is needed it has to be enabled again.
802		if (tc) {
803		BIT_CLR(m_flags , HPHYBRID_DMAEN_BIT);
804		}
	799	// This is the one of the biggest question marks: is the DMA automatically disabled on TC?
	800	// Here we assume it is. After all it would make no difference because there is no way
	801	// to read the DMA enable flag back, so each time the DMA is needed it has to be enabled again.
	802	if (tc) {
	803	BIT_CLR(m_flags , HPHYBRID_DMAEN_BIT);
	804	}
805	805	}
806	806
807	807	UINT16 hp_hybrid_cpu_device::RM(UINT16 addr)
808	808	{
809		UINT16 tmp;
	809	UINT16 tmp;
810	810
811		if (addr <= HP_REG_LAST_ADDR) {
812		// Memory mapped registers
813		switch (addr) {
814		case HP_REG_A_ADDR:
815		return m_reg_A;
	811	if (addr <= HP_REG_LAST_ADDR) {
	812	// Memory mapped registers
	813	switch (addr) {
	814	case HP_REG_A_ADDR:
	815	return m_reg_A;
816	816
817		case HP_REG_B_ADDR:
818		return m_reg_B;
	817	case HP_REG_B_ADDR:
	818	return m_reg_B;
819	819
820		case HP_REG_P_ADDR:
821		return m_reg_P;
	820	case HP_REG_P_ADDR:
	821	return m_reg_P;
822	822
823		case HP_REG_R_ADDR:
824		return m_reg_R;
	823	case HP_REG_R_ADDR:
	824	return m_reg_R;
825	825
826		case HP_REG_R4_ADDR:
827		case HP_REG_R5_ADDR:
828		case HP_REG_R6_ADDR:
829		case HP_REG_R7_ADDR:
830		return RIO(CURRENT_PA , addr - HP_REG_R4_ADDR);
	826	case HP_REG_R4_ADDR:
	827	case HP_REG_R5_ADDR:
	828	case HP_REG_R6_ADDR:
	829	case HP_REG_R7_ADDR:
	830	return RIO(CURRENT_PA , addr - HP_REG_R4_ADDR);
831	831
832		case HP_REG_IV_ADDR:
833		// Correct?
834		if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
835		return m_reg_IV;
836		} else {
837		return m_reg_IV \| CURRENT_PA;
838		}
	832	case HP_REG_IV_ADDR:
	833	// Correct?
	834	if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
	835	return m_reg_IV;
	836	} else {
	837	return m_reg_IV \| CURRENT_PA;
	838	}
839	839
840		case HP_REG_PA_ADDR:
841		return CURRENT_PA;
	840	case HP_REG_PA_ADDR:
	841	return CURRENT_PA;
842	842
843		case HP_REG_DMAPA_ADDR:
844		tmp = m_dmapa & HP_REG_PA_MASK;
845		if (BIT(m_flags , HPHYBRID_CB_BIT)) {
846		BIT_SET(tmp , 15);
847		}
848		if (BIT(m_flags , HPHYBRID_DB_BIT)) {
849		BIT_SET(tmp , 14);
850		}
851		return tmp;
	843	case HP_REG_DMAPA_ADDR:
	844	tmp = m_dmapa & HP_REG_PA_MASK;
	845	if (BIT(m_flags , HPHYBRID_CB_BIT)) {
	846	BIT_SET(tmp , 15);
	847	}
	848	if (BIT(m_flags , HPHYBRID_DB_BIT)) {
	849	BIT_SET(tmp , 14);
	850	}
	851	return tmp;
852	852
853		case HP_REG_DMAMA_ADDR:
854		return m_dmama;
	853	case HP_REG_DMAMA_ADDR:
	854	return m_dmama;
855	855
856		case HP_REG_DMAC_ADDR:
857		return m_dmac;
	856	case HP_REG_DMAC_ADDR:
	857	return m_dmac;
858	858
859		case HP_REG_C_ADDR:
860		return m_reg_C;
	859	case HP_REG_C_ADDR:
	860	return m_reg_C;
861	861
862		case HP_REG_D_ADDR:
863		return m_reg_D;
	862	case HP_REG_D_ADDR:
	863	return m_reg_D;
864	864
865		default:
866		// Unknown registers are returned as 0
867		return 0;
868		}
869		} else {
870		return m_direct->read_word((offs_t)addr << 1);
871		}
	865	default:
	866	// Unknown registers are returned as 0
	867	return 0;
	868	}
	869	} else {
	870	return m_direct->read_word((offs_t)addr << 1);
	871	}
872	872	}
873	873
874	874	void hp_hybrid_cpu_device::WM(UINT16 addr , UINT16 v)
875	875	{
876		if (addr <= HP_REG_LAST_ADDR) {
877		// Memory mapped registers
878		switch (addr) {
879		case HP_REG_A_ADDR:
880		m_reg_A = v;
881		break;
	876	if (addr <= HP_REG_LAST_ADDR) {
	877	// Memory mapped registers
	878	switch (addr) {
	879	case HP_REG_A_ADDR:
	880	m_reg_A = v;
	881	break;
882	882
883		case HP_REG_B_ADDR:
884		m_reg_B = v;
885		break;
	883	case HP_REG_B_ADDR:
	884	m_reg_B = v;
	885	break;
886	886
887		case HP_REG_P_ADDR:
888		m_reg_P = v;
889		break;
	887	case HP_REG_P_ADDR:
	888	m_reg_P = v;
	889	break;
890	890
891		case HP_REG_R_ADDR:
892		m_reg_R = v;
893		break;
	891	case HP_REG_R_ADDR:
	892	m_reg_R = v;
	893	break;
894	894
895		case HP_REG_R4_ADDR:
896		case HP_REG_R5_ADDR:
897		case HP_REG_R6_ADDR:
898		case HP_REG_R7_ADDR:
899		WIO(CURRENT_PA , addr - HP_REG_R4_ADDR , v);
900		break;
	895	case HP_REG_R4_ADDR:
	896	case HP_REG_R5_ADDR:
	897	case HP_REG_R6_ADDR:
	898	case HP_REG_R7_ADDR:
	899	WIO(CURRENT_PA , addr - HP_REG_R4_ADDR , v);
	900	break;
901	901
902		case HP_REG_IV_ADDR:
903		m_reg_IV = v & HP_REG_IV_MASK;
904		break;
	902	case HP_REG_IV_ADDR:
	903	m_reg_IV = v & HP_REG_IV_MASK;
	904	break;
905	905
906		case HP_REG_PA_ADDR:
907		CURRENT_PA = v & HP_REG_PA_MASK;
908		break;
	906	case HP_REG_PA_ADDR:
	907	CURRENT_PA = v & HP_REG_PA_MASK;
	908	break;
909	909
910		case HP_REG_DMAPA_ADDR:
911		m_dmapa = v & HP_REG_PA_MASK;
912		break;
	910	case HP_REG_DMAPA_ADDR:
	911	m_dmapa = v & HP_REG_PA_MASK;
	912	break;
913	913
914		case HP_REG_DMAMA_ADDR:
915		m_dmama = v;
916		break;
	914	case HP_REG_DMAMA_ADDR:
	915	m_dmama = v;
	916	break;
917	917
918		case HP_REG_DMAC_ADDR:
919		m_dmac = v;
920		break;
	918	case HP_REG_DMAC_ADDR:
	919	m_dmac = v;
	920	break;
921	921
922		case HP_REG_C_ADDR:
923		m_reg_C = v;
924		break;
	922	case HP_REG_C_ADDR:
	923	m_reg_C = v;
	924	break;
925	925
926		case HP_REG_D_ADDR:
927		m_reg_D = v;
928		break;
	926	case HP_REG_D_ADDR:
	927	m_reg_D = v;
	928	break;
929	929
930		default:
931		// Unknown registers are silently discarded
932		break;
933		}
934		} else {
935		m_program->write_word((offs_t)addr << 1 , v);
936		}
	930	default:
	931	// Unknown registers are silently discarded
	932	break;
	933	}
	934	} else {
	935	m_program->write_word((offs_t)addr << 1 , v);
	936	}
937	937	}
938	938
939	939	void hp_hybrid_cpu_device::WMB(UINT32 addr , UINT8 v)
940	940	{
941		if (addr <= (HP_REG_LAST_ADDR * 2 + 1)) {
942		// Cannot write bytes to registers
943		} else {
944		m_program->write_byte(addr , v);
945		}
	941	if (addr <= (HP_REG_LAST_ADDR * 2 + 1)) {
	942	// Cannot write bytes to registers
	943	} else {
	944	m_program->write_byte(addr , v);
	945	}
946	946	}
947	947
948	948	UINT16 hp_hybrid_cpu_device::RIO(UINT8 pa , UINT8 ic)
949	949	{
950		return m_io->read_word(HP_MAKE_IOADDR(pa, ic) << 1);
	950	return m_io->read_word(HP_MAKE_IOADDR(pa, ic) << 1);
951	951	}
952	952
953	953	void hp_hybrid_cpu_device::WIO(UINT8 pa , UINT8 ic , UINT16 v)
954	954	{
955		m_io->write_word(HP_MAKE_IOADDR(pa, ic) << 1 , v);
	955	m_io->write_word(HP_MAKE_IOADDR(pa, ic) << 1 , v);
956	956	}
957	957
958	958	hp_5061_3011_cpu_device::hp_5061_3011_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)

trunk/src/emu/cpu/hphybrid/hphybrid.h
r248551	r248552
65	65	class hp_hybrid_cpu_device : public cpu_device
66	66	{
67	67	public:
68		DECLARE_WRITE_LINE_MEMBER(dmar_w);
	68	DECLARE_WRITE_LINE_MEMBER(dmar_w);
69	69
70	70	protected:
71	71	hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname);
r248551	r248552
126	126	UINT16 get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n);
127	127	void do_pw(UINT16 opcode);
128	128	void check_for_interrupts(void);
129		void handle_dma(void);
	129	void handle_dma(void);
130	130
131	131	UINT16 RM(UINT16 addr);
132	132	void WM(UINT16 addr , UINT16 v);

trunk/src/emu/cpu/m68000/m68kcpu.c
r248551	r248552
2336	2336
2337	2337	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
2338	2338	: cpu_device(mconfig, M68K, "M68K", tag, owner, clock, "m68k", __FILE__),
2339		m_program_config("program", ENDIANNESS_BIG, 16, 24),
2340		m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, 16, 24)
	2339	m_program_config("program", ENDIANNESS_BIG, 16, 24),
	2340	m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, 16, 24)
2341	2341	{
2342	2342	clear_all();
2343	2343	}
r248551	r248552
2348	2348	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
2349	2349	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char shortname, const char source)
2350	2350	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
2351		m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map),
2352		m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map)
	2351	m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map),
	2352	m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map)
2353	2353	{
2354	2354	clear_all();
2355	2355	}
r248551	r248552
2358	2358	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
2359	2359	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, const char shortname, const char source)
2360	2360	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
2361		m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits),
2362		m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits)
	2361	m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits),
	2362	m_oprogram_config("decrypted_opcodes", ENDIANNESS_BIG, prg_data_width, prg_address_bits)
2363	2363	{
2364	2364	clear_all();
2365	2365	}

trunk/src/emu/cpu/rsp/rsp.c
r248551	r248552
801	801	m_rsp_state->icount = MIN(m_rsp_state->icount, 0);
802	802	}
803	803	/*m_cop2->dump(op);
804		if (((op >> 26) & 0x3f) == 0x3a)
805		{
806		m_cop2->dump_dmem();
807		}*/
	804	if (((op >> 26) & 0x3f) == 0x3a)
	805	{
	806	m_cop2->dump_dmem();
	807	}*/
808	808	}
809	809	}

trunk/src/emu/cpu/rsp/rspcp2.c
r248551	r248552
206	206	{ 0xffff, 0xffff, 0x0000, 0x0000 }, // L
207	207	{ 0xffff, 0xffff, 0xffff, 0xffff } // D
208	208	},
209		{ // word_reverse
210		0x0203, 0x0001, 0x0607, 0x0405, 0x0a0b, 0x0809, 0x0e0f, 0x0c0d
211		}
	209	{ // word_reverse
	210	0x0203, 0x0001, 0x0607, 0x0405, 0x0a0b, 0x0809, 0x0e0f, 0x0c0d
	211	}
212	212	};
213	213
214	214	#if !(defined(__SSSE3__) \|\| defined(_MSC_VER))
r248551	r248552
322	322	dqm = _mm_shuffle_epi8(dqm, ekey);
323	323	#endif
324	324
325		// Align the data to the DQM so we can mask it in.
	325	// Align the data to the DQM so we can mask it in.
326	326	#if !(defined(__SSSE3__) \|\| defined(_MSC_VER))
327	327	data = sse2_pshufb(data, m_vec_helpers.ror_b2l_keys[ror & 0xF]);
328	328	#else
r248551	r248552
330	330	data = _mm_shuffle_epi8(data, ekey);
331	331	#endif
332	332
333		// Mask and mux in the data.
	333	// Mask and mux in the data.
334	334	#if (defined(__SSE4_1__) \|\| defined(_MSC_VER))
335	335	reg = _mm_blendv_epi8(reg, data, dqm);
336	336	#else
r248551	r248552
377	377	}
378	378
379	379	// "Unpack" the data.
380		rsp_vec_t zero = _mm_setzero_si128();
	380	rsp_vec_t zero = _mm_setzero_si128();
381	381	data = _mm_unpacklo_epi8(zero, data);
382	382
383	383	if (request_type != RSP_MEM_REQUEST_PACK)
r248551	r248552
385	385	data = _mm_srli_epi16(data, 1);
386	386	}
387	387
388		data = _mm_shufflehi_epi16(data, _MM_SHUFFLE(0, 1, 2, 3));
389		data = _mm_shufflelo_epi16(data, _MM_SHUFFLE(0, 1, 2, 3));
	388	data = _mm_shufflehi_epi16(data, _MM_SHUFFLE(0, 1, 2, 3));
	389	data = _mm_shufflelo_epi16(data, _MM_SHUFFLE(0, 1, 2, 3));
390	390
391		_mm_store_si128((rsp_vec_t *) regp, data);
	391	_mm_store_si128((rsp_vec_t *) regp, data);
392	392	}
393	393
394	394	//
r248551	r248552
403	403	{
404	404	UINT32 aligned_addr = addr & 0xFF0;
405	405	UINT32 offset = addr & 0xF;
406		static UINT32 call_count = 0;
	406	static UINT32 call_count = 0;
407	407
408	408	rsp_vec_t data = _mm_load_si128((rsp_vec_t *) (m_rsp.get_dmem() + aligned_addr));
409	409
r248551	r248552
439	439
440	440	_mm_store_si128((rsp_vec_t *) regp, data);
441	441
442		call_count++;
	442	call_count++;
443	443	}
444	444
445	445	//
r248551	r248552
542	542	reg = _mm_shuffle_epi8(reg, dkey);
543	543	#endif
544	544
545		// TODO: Always store in 8-byte chunks to emulate wraparound.
	545	// TODO: Always store in 8-byte chunks to emulate wraparound.
546	546	_mm_storel_epi64((rsp_vec_t *) (m_rsp.get_dmem() + addr), reg);
547	547	}
548	548
r248551	r248552
574	574	reg = _mm_shuffle_epi8(reg, ekey);
575	575	#endif
576	576
577		// Mask and mux out the data, write.
	577	// Mask and mux out the data, write.
578	578	#if (defined(__SSE4_1__) \|\| defined(_MSC_VER))
579	579	data = _mm_blendv_epi8(data, reg, dqm);
580	580	#else
r248551	r248552
702	702	memset(m_vflag, 0, sizeof(m_vflag));
703	703	memset(m_accum, 0, sizeof(m_accum));
704	704	#if USE_SIMD
705		memset(&m_acc, 0, sizeof(m_acc));
706		memset(&m_flags, 0, sizeof(aligned_rsp_2vect_t) * 3);
707		m_div_out = 0;
708		m_div_in = 0;
	705	memset(&m_acc, 0, sizeof(m_acc));
	706	memset(&m_flags, 0, sizeof(aligned_rsp_2vect_t) * 3);
	707	m_div_out = 0;
	708	m_div_in = 0;
709	709	#endif
710	710	m_rspcop2_state = (internal_rspcop2_state *)rsp.m_cache.alloc_near(sizeof(internal_rspcop2_state));
711	711	}
r248551	r248552
877	877	//
878	878	// Load 1 byte to vector byte index
879	879
880		//printf("LBV ");
	880	//printf("LBV ");
881	881	#if USE_SIMD
882	882	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
883	883	#else
r248551	r248552
896	896	//
897	897	// Loads 2 bytes starting from vector byte index
898	898
899		//printf("LSV ");
	899	//printf("LSV ");
900	900	#if USE_SIMD
901	901	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
902	902	#else
r248551	r248552
922	922	//
923	923	// Loads 4 bytes starting from vector byte index
924	924
925		//printf("LLV ");
	925	//printf("LLV ");
926	926	#if USE_SIMD
927	927	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
928	928	#else
r248551	r248552
948	948	//
949	949	// Loads 8 bytes starting from vector byte index
950	950
951		//printf("LDV ");
	951	//printf("LDV ");
952	952	#if USE_SIMD
953	953	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
954	954	#else
r248551	r248552
974	974	//
975	975	// Loads up to 16 bytes starting from vector byte index
976	976
977		//printf("LQV ");
	977	//printf("LQV ");
978	978	#if USE_SIMD
979	979	vec_lqrv_sqrv(op, m_rsp.m_rsp_state->r[base]);
980	980	#else
r248551	r248552
1001	1001	//
1002	1002	// Stores up to 16 bytes starting from right side until 16-byte boundary
1003	1003
1004		//printf("LRV ");
	1004	//printf("LRV ");
1005	1005	#if USE_SIMD
1006	1006	vec_lqrv_sqrv(op, m_rsp.m_rsp_state->r[base]);
1007	1007	#else
r248551	r248552
1029	1029	//
1030	1030	// Loads a byte as the upper 8 bits of each element
1031	1031
1032		//printf("LPV ");
	1032	//printf("LPV ");
1033	1033	#if USE_SIMD
1034	1034	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1035	1035	#else
r248551	r248552
1052	1052	//
1053	1053	// Loads a byte as the bits 14-7 of each element
1054	1054
1055		//printf("LUV ");
	1055	//printf("LUV ");
1056	1056	#if USE_SIMD
1057	1057	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1058	1058	#else
r248551	r248552
1075	1075	//
1076	1076	// Loads a byte as the bits 14-7 of each element, with 2-byte stride
1077	1077
1078		//printf("LHV ");
	1078	//printf("LHV ");
1079	1079	#if USE_SIMD
1080	1080	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1081	1081	#else
r248551	r248552
1098	1098	//
1099	1099	// Loads a byte as the bits 14-7 of upper or lower quad, with 4-byte stride
1100	1100
1101		//printf("LFV ");
	1101	//printf("LFV ");
1102	1102	#if USE_SIMD
1103	1103	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1104	1104	#else
r248551	r248552
1127	1127	// Loads the full 128-bit vector starting from vector byte index and wrapping to index 0
1128	1128	// after byte index 15
1129	1129
1130		//printf("LWV ");
	1130	//printf("LWV ");
1131	1131	#if USE_SIMD
1132	1132	#else
1133	1133	ea = (base) ? m_rsp.m_rsp_state->r[base] + (offset * 16) : (offset * 16);
r248551	r248552
1154	1154
1155	1155	// FIXME: has a small problem with odd indices
1156	1156
1157		//printf("LTV ");
	1157	//printf("LTV ");
1158	1158	#if 0
1159	1159	#else
1160		INT32 index = (op >> 7) & 0xf;
1161		INT32 offset = (op & 0x7f);
1162		if (offset & 0x40)
1163		offset \|= 0xffffffc0;
	1160	INT32 index = (op >> 7) & 0xf;
	1161	INT32 offset = (op & 0x7f);
	1162	if (offset & 0x40)
	1163	offset \|= 0xffffffc0;
1164	1164
1165		INT32 vs = (op >> 16) & 0x1f;
	1165	INT32 vs = (op >> 16) & 0x1f;
1166	1166	INT32 ve = vs + 8;
1167	1167	if (ve > 32)
1168	1168	ve = 32;
r248551	r248552
1225	1225	//
1226	1226	// Stores 1 byte from vector byte index
1227	1227
1228		//printf("SBV ");
	1228	//printf("SBV ");
1229	1229	#if USE_SIMD
1230	1230	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
1231	1231	#else
r248551	r248552
1244	1244	//
1245	1245	// Stores 2 bytes starting from vector byte index
1246	1246
1247		//printf("SSV ");
	1247	//printf("SSV ");
1248	1248	#if USE_SIMD
1249	1249	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
1250	1250	#else
r248551	r248552
1270	1270	//
1271	1271	// Stores 4 bytes starting from vector byte index
1272	1272
1273		//printf("SLV ");
	1273	//printf("SLV ");
1274	1274	#if USE_SIMD
1275	1275	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
1276	1276	#else
r248551	r248552
1296	1296	//
1297	1297	// Stores 8 bytes starting from vector byte index
1298	1298
1299		//printf("SDV ");
	1299	//printf("SDV ");
1300	1300	#if USE_SIMD
1301	1301	vec_lbdlsv_sbdlsv(op, m_rsp.m_rsp_state->r[base]);
1302	1302	#else
r248551	r248552
1322	1322	//
1323	1323	// Stores up to 16 bytes starting from vector byte index until 16-byte boundary
1324	1324
1325		//printf("SQV ");
	1325	//printf("SQV ");
1326	1326	#if USE_SIMD
1327	1327	vec_lqrv_sqrv(op, m_rsp.m_rsp_state->r[base]);
1328	1328	#else
r248551	r248552
1348	1348	//
1349	1349	// Stores up to 16 bytes starting from right side until 16-byte boundary
1350	1350
1351		//printf("SRV ");
	1351	//printf("SRV ");
1352	1352	#if USE_SIMD
1353	1353	vec_lqrv_sqrv(op, m_rsp.m_rsp_state->r[base]);
1354	1354	#else
r248551	r248552
1377	1377	//
1378	1378	// Stores upper 8 bits of each element
1379	1379
1380		//printf("SPV ");
	1380	//printf("SPV ");
1381	1381	#if USE_SIMD
1382	1382	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1383	1383	#else
r248551	r248552
1409	1409	//
1410	1410	// Stores bits 14-7 of each element
1411	1411
1412		//printf("SUV ");
	1412	//printf("SUV ");
1413	1413	#if USE_SIMD
1414	1414	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1415	1415	#else
r248551	r248552
1441	1441	//
1442	1442	// Stores bits 14-7 of each element, with 2-byte stride
1443	1443
1444		//printf("SHV ");
	1444	//printf("SHV ");
1445	1445	#if USE_SIMD
1446	1446	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1447	1447	#else
r248551	r248552
1470	1470
1471	1471	// FIXME: only works for index 0 and index 8
1472	1472
1473		//printf("SFV ");
	1473	//printf("SFV ");
1474	1474	#if USE_SIMD
1475	1475	vec_lfhpuv_sfhpuv(op, m_rsp.m_rsp_state->r[base]);
1476	1476	#else
r248551	r248552
1500	1500	// Stores the full 128-bit vector starting from vector byte index and wrapping to index 0
1501	1501	// after byte index 15
1502	1502
1503		//printf("SWV ");
	1503	//printf("SWV ");
1504	1504	#if USE_SIMD
1505	1505	#else
1506	1506	ea = (base) ? m_rsp.m_rsp_state->r[base] + (offset * 16) : (offset * 16);
r248551	r248552
1528	1528	//
1529	1529	// Stores one element from maximum of 8 vectors, while incrementing element index
1530	1530
1531		//printf("STV ");
	1531	//printf("STV ");
1532	1532	#if 0
1533	1533	#else
1534		INT32 index = (op >> 7) & 0xf;
1535		INT32 offset = (op & 0x7f);
1536		if (offset & 0x40)
1537		offset \|= 0xffffffc0;
	1534	INT32 index = (op >> 7) & 0xf;
	1535	INT32 offset = (op & 0x7f);
	1536	if (offset & 0x40)
	1537	offset \|= 0xffffffc0;
1538	1538
1539	1539	INT32 vs = (op >> 16) & 0x1f;
1540	1540	INT32 ve = vs + 8;
r248551	r248552
1548	1548	INT32 eaoffset = (ea & 0xf) + (element * 2);
1549	1549	ea &= ~0xf;
1550	1550
1551		for (INT32 i = vs; i < ve; i++)
	1551	for (INT32 i = vs; i < ve; i++)
1552	1552	{
1553	1553	m_rsp.WRITE16(ea + (eaoffset & 0xf), VREG_S(i, element & 0x7));
1554	1554	eaoffset += 2;
r248551	r248552
1654	1654	//
1655	1655	// Multiplies signed integer by signed integer * 2
1656	1656
1657		//printf("MULF ");
	1657	//printf("MULF ");
1658	1658	#if USE_SIMD
1659	1659	UINT16 *acc = m_acc.s;
1660	1660	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
1706	1706	// ------------------------------------------------------
1707	1707	//
1708	1708
1709		//printf("MULU ");
	1709	//printf("MULU ");
1710	1710	#if USE_SIMD
1711	1711	UINT16 *acc = m_acc.s;
1712	1712	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
1762	1762	// Stores the higher 16 bits of the 32-bit result to accumulator
1763	1763	// The low slice of accumulator is stored into destination element
1764	1764
1765		//printf("MUDL ");
	1765	//printf("MUDL ");
1766	1766	#if USE_SIMD
1767	1767	UINT16 *acc = m_acc.s;
1768	1768	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
1809	1809	// The result is stored into accumulator
1810	1810	// The middle slice of accumulator is stored into destination element
1811	1811
1812		//printf("MUDM ");
	1812	//printf("MUDM ");
1813	1813	#if USE_SIMD
1814	1814	UINT16 *acc = m_acc.s;
1815	1815	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
1857	1857	// The result is stored into accumulator
1858	1858	// The low slice of accumulator is stored into destination element
1859	1859
1860		//printf("MUDN ");
	1860	//printf("MUDN ");
1861	1861	#if USE_SIMD
1862	1862	UINT16 *acc = m_acc.s;
1863	1863	rsp_vec_t acc_lo = read_acc_lo(acc);
r248551	r248552
1902	1902	// The result is stored into highest 32 bits of accumulator, the low slice is zero
1903	1903	// The highest 32 bits of accumulator is saturated into destination element
1904	1904
1905		//printf("MUDH ");
	1905	//printf("MUDH ");
1906	1906	#if USE_SIMD
1907	1907	UINT16 *acc = m_acc.s;
1908	1908	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
1950	1950	// Multiplies signed integer by signed integer * 2
1951	1951	// The result is added to accumulator
1952	1952
1953		//printf("MACF ");
	1953	//printf("MACF ");
1954	1954	#if USE_SIMD
1955	1955	UINT16 *acc = m_acc.s;
1956	1956	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2001	2001	// ------------------------------------------------------
2002	2002	//
2003	2003
2004		//printf("MACU ");
	2004	//printf("MACU ");
2005	2005	#if USE_SIMD
2006	2006	UINT16 *acc = m_acc.s;
2007	2007	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2071	2071	// Adds the higher 16 bits of the 32-bit result to accumulator
2072	2072	// The low slice of accumulator is stored into destination element
2073	2073
2074		//printf("MADL ");
	2074	//printf("MADL ");
2075	2075	#if USE_SIMD
2076	2076	UINT16 *acc = m_acc.s;
2077	2077	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2120	2120	// The result is added into accumulator
2121	2121	// The middle slice of accumulator is stored into destination element
2122	2122
2123		//printf("MADM ");
	2123	//printf("MADM ");
2124	2124	#if USE_SIMD
2125	2125	UINT16 *acc = m_acc.s;
2126	2126	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2171	2171	// The result is added into accumulator
2172	2172	// The low slice of accumulator is stored into destination element
2173	2173
2174		//printf("MADN ");
	2174	//printf("MADN ");
2175	2175	#if USE_SIMD
2176	2176	UINT16 *acc = m_acc.s;
2177	2177	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2225	2225	// The result is added into highest 32 bits of accumulator, the low slice is zero
2226	2226	// The highest 32 bits of accumulator is saturated into destination element
2227	2227
2228		//printf("MADH ");
	2228	//printf("MADH ");
2229	2229	#if USE_SIMD
2230	2230	UINT16 *acc = m_acc.s;
2231	2231	rsp_vec_t acc_lo, acc_mid, acc_hi;
r248551	r248552
2275	2275
2276	2276	// TODO: check VS2REG == VDREG
2277	2277
2278		//printf("ADD ");
	2278	//printf("ADD ");
2279	2279	#if USE_SIMD
2280	2280	rsp_vec_t acc_lo;
2281	2281	UINT16 *acc = m_acc.s;
r248551	r248552
2321	2321
2322	2322	// TODO: check VS2REG == VDREG
2323	2323
2324		//printf("SUB ");
	2324	//printf("SUB ");
2325	2325	#if USE_SIMD
2326	2326	rsp_vec_t acc_lo;
2327	2327	UINT16 *acc = m_acc.s;
r248551	r248552
2367	2367	// Changes the sign of source register 2 if source register 1 is negative and stores
2368	2368	// the result to destination register
2369	2369
2370		//printf("ABS ");
	2370	//printf("ABS ");
2371	2371	#if USE_SIMD
2372	2372	rsp_vec_t acc_lo;
2373	2373	UINT16 *acc = m_acc.s;
r248551	r248552
2423	2423
2424	2424	// TODO: check VS2REG = VDREG
2425	2425
2426		//printf("ADDC ");
	2426	//printf("ADDC ");
2427	2427	#if USE_SIMD
2428	2428	UINT16 *acc = m_acc.s;
2429	2429	rsp_vec_t sn;
r248551	r248552
2471	2471
2472	2472	// TODO: check VS2REG = VDREG
2473	2473
2474		//printf("SUBC ");
	2474	//printf("SUBC ");
2475	2475	#if USE_SIMD
2476	2476	UINT16 *acc = m_acc.s;
2477	2477	rsp_vec_t eq, sn;
r248551	r248552
2521	2521	//
2522	2522	// Stores high, middle or low slice of accumulator to destination vector
2523	2523
2524		//printf("SAW ");
	2524	//printf("SAW ");
2525	2525	#if USE_SIMD
2526	2526	UINT16 *acc = m_acc.s;
2527	2527	switch (EL)
r248551	r248552
2586	2586	// Sets compare flags if elements in VS1 are less than VS2
2587	2587	// Moves the element in VS2 to destination vector
2588	2588
2589		//printf("LT ");
	2589	//printf("LT ");
2590	2590	#if USE_SIMD
2591	2591	UINT16 *acc = m_acc.s;
2592	2592	rsp_vec_t le;
r248551	r248552
2655	2655	// Sets compare flags if elements in VS1 are equal with VS2
2656	2656	// Moves the element in VS2 to destination vector
2657	2657
2658		//printf("EQ ");
	2658	//printf("EQ ");
2659	2659	#if USE_SIMD
2660	2660	UINT16 *acc = m_acc.s;
2661	2661	rsp_vec_t le;
r248551	r248552
2712	2712	// Sets compare flags if elements in VS1 are not equal with VS2
2713	2713	// Moves the element in VS2 to destination vector
2714	2714
2715		//printf("NE ");
	2715	//printf("NE ");
2716	2716	#if USE_SIMD
2717	2717	UINT16 *acc = m_acc.s;
2718	2718	rsp_vec_t le;
r248551	r248552
2770	2770	// Sets compare flags if elements in VS1 are greater or equal with VS2
2771	2771	// Moves the element in VS2 to destination vector
2772	2772
2773		//printf("GE ");
	2773	//printf("GE ");
2774	2774	#if USE_SIMD
2775	2775	UINT16 *acc = m_acc.s;
2776	2776	rsp_vec_t le;
r248551	r248552
2827	2827	//
2828	2828	// Vector clip low
2829	2829
2830		//printf("CL ");
	2830	//printf("CL ");
2831	2831	#if USE_SIMD
2832	2832	UINT16 *acc = m_acc.s;
2833	2833
r248551	r248552
2944	2944	//
2945	2945	// Vector clip high
2946	2946
2947		//printf("CH ");
	2947	//printf("CH ");
2948	2948	#if USE_SIMD
2949	2949	UINT16 *acc = m_acc.s;
2950	2950	rsp_vec_t ge, le, sign, eq, vce;
r248551	r248552
3047	3047	//
3048	3048	// Vector clip reverse
3049	3049
3050		//printf("CR ");
	3050	//printf("CR ");
3051	3051	#if USE_SIMD
3052	3052	UINT16 *acc = m_acc.s;
3053	3053	rsp_vec_t ge, le;
r248551	r248552
3125	3125	//
3126	3126	// Merges two vectors according to compare flags
3127	3127
3128		//printf("MRG ");
	3128	//printf("MRG ");
3129	3129	#if USE_SIMD
3130	3130	UINT16 *acc = m_acc.s;
3131	3131	rsp_vec_t le = read_vcc_lo(m_flags[RSP_VCC].s);
r248551	r248552
3166	3166	//
3167	3167	// Bitwise AND of two vector registers
3168	3168
3169		//printf("AND ");
	3169	//printf("AND ");
3170	3170	#if USE_SIMD
3171	3171	UINT16 *acc = m_acc.s;
3172	3172
r248551	r248552
3196	3196	//
3197	3197	// Bitwise NOT AND of two vector registers
3198	3198
3199		//printf("NAND ");
	3199	//printf("NAND ");
3200	3200	#if USE_SIMD
3201	3201	UINT16 *acc = m_acc.s;
3202	3202
r248551	r248552
3226	3226	//
3227	3227	// Bitwise OR of two vector registers
3228	3228
3229		//printf("OR ");
	3229	//printf("OR ");
3230	3230	#if USE_SIMD
3231	3231	UINT16 *acc = m_acc.s;
3232	3232
r248551	r248552
3256	3256	//
3257	3257	// Bitwise NOT OR of two vector registers
3258	3258
3259		//printf("NOR ");
	3259	//printf("NOR ");
3260	3260	#if USE_SIMD
3261	3261	UINT16 *acc = m_acc.s;
3262	3262
r248551	r248552
3286	3286	//
3287	3287	// Bitwise XOR of two vector registers
3288	3288
3289		//printf("XOR ");
	3289	//printf("XOR ");
3290	3290	#if USE_SIMD
3291	3291	UINT16 *acc = m_acc.s;
3292	3292
r248551	r248552
3316	3316	//
3317	3317	// Bitwise NOT XOR of two vector registers
3318	3318
3319		//printf("NXOR ");
	3319	//printf("NXOR ");
3320	3320	#if USE_SIMD
3321	3321	UINT16 *acc = m_acc.s;
3322	3322
r248551	r248552
3347	3347	//
3348	3348	// Calculates reciprocal
3349	3349
3350		//printf("RCP ");
	3350	//printf("RCP ");
3351	3351	#if USE_SIMD
3352	3352	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3353	3353
r248551	r248552
3418	3418	//
3419	3419	// Calculates reciprocal low part
3420	3420
3421		//printf("RCPL ");
	3421	//printf("RCPL ");
3422	3422	#if USE_SIMD
3423	3423	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3424	3424
r248551	r248552
3505	3505	//
3506	3506	// Calculates reciprocal high part
3507	3507
3508		//printf("RCPH ");
	3508	//printf("RCPH ");
3509	3509	#if USE_SIMD
3510	3510	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3511	3511
r248551	r248552
3537	3537	//
3538	3538	// Moves element from vector to destination vector
3539	3539
3540		//printf("MOV ");
	3540	//printf("MOV ");
3541	3541	#if USE_SIMD
3542	3542	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3543	3543	m_v[VDREG].v = vec_vmov(VS2REG, EL, VDREG, VS1REG);
r248551	r248552
3561	3561	//
3562	3562	// Calculates reciprocal square-root
3563	3563
3564		//printf("RSQ ");
	3564	//printf("RSQ ");
3565	3565	#if USE_SIMD
3566	3566	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3567	3567
r248551	r248552
3633	3633	//
3634	3634	// Calculates reciprocal square-root low part
3635	3635
3636		//printf("RSQL ");
	3636	//printf("RSQL ");
3637	3637	#if USE_SIMD
3638	3638	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3639	3639
r248551	r248552
3723	3723	//
3724	3724	// Calculates reciprocal square-root high part
3725	3725
3726		//printf("RSQH ");
	3726	//printf("RSQH ");
3727	3727	#if USE_SIMD
3728	3728	write_acc_lo(m_acc.s, vec_load_and_shuffle_operand(m_v[VS2REG].s, EL));
3729	3729
r248551	r248552
3754	3754	//
3755	3755	// Vector null instruction
3756	3756
3757		//printf("NOP ");
	3757	//printf("NOP ");
3758	3758	break;
3759	3759	}
3760	3760
r248551	r248552
3777	3777	// \| 010010 \| 00000 \| TTTTT \| DDDDD \| IIII \| 0000000 \|
3778	3778	// ---------------------------------------------------
3779	3779	//
3780		//printf("MFC2 ");
	3780	//printf("MFC2 ");
3781	3781	int el = (op >> 7) & 0xf;
3782	3782	UINT16 b1 = VREG_B(RDREG, (el+0) & 0xf);
3783	3783	UINT16 b2 = VREG_B(RDREG, (el+1) & 0xf);
r248551	r248552
3792	3792	// \| 010010 \| 00010 \| TTTTT \| DDDDD \| 00000000000 \|
3793	3793	// ------------------------------------------------
3794	3794	//
3795		//printf("CFC2 ");
	3795	//printf("CFC2 ");
3796	3796	if (RTREG)
3797	3797	{
3798	3798	#if USE_SIMD
3799		INT32 src = RDREG & 3;
3800		if (src == 3) {
3801		src = 2;
3802		}
3803		RTVAL = get_flags(m_flags[src].s);
	3799	INT32 src = RDREG & 3;
	3800	if (src == 3) {
	3801	src = 2;
	3802	}
	3803	RTVAL = get_flags(m_flags[src].s);
3804	3804	#else
3805	3805	switch(RDREG)
3806	3806	{
r248551	r248552
3865	3865	// \| 010010 \| 00100 \| TTTTT \| DDDDD \| IIII \| 0000000 \|
3866	3866	// ---------------------------------------------------
3867	3867	//
3868		//printf("MTC2 ");
	3868	//printf("MTC2 ");
3869	3869	int el = (op >> 7) & 0xf;
3870	3870	W_VREG_B(RDREG, (el+0) & 0xf, (RTVAL >> 8) & 0xff);
3871	3871	W_VREG_B(RDREG, (el+1) & 0xf, (RTVAL >> 0) & 0xff);
r248551	r248552
3966	3966	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
3967	3967	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
3968	3968	{
3969		//printf("V");
	3969	//printf("V");
3970	3970	handle_vector_ops(op);
3971	3971	break;
3972	3972	}
r248551	r248552
4185	4185	}
4186	4186
4187	4187	#if USE_SIMD
4188		printf("acc_h: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[0], m_acc.s[1], m_acc.s[2], m_acc.s[3], m_acc.s[4], m_acc.s[5], m_acc.s[6], m_acc.s[7]);
4189		printf("acc_m: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[8], m_acc.s[9], m_acc.s[10], m_acc.s[11], m_acc.s[12], m_acc.s[13], m_acc.s[14], m_acc.s[15]);
4190		printf("acc_l: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[16], m_acc.s[17], m_acc.s[18], m_acc.s[19], m_acc.s[20], m_acc.s[21], m_acc.s[22], m_acc.s[23]);
4191		printf("vcc_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCC].s[0], m_flags[RSP_VCC].s[1], m_flags[RSP_VCC].s[2], m_flags[RSP_VCC].s[3], m_flags[RSP_VCC].s[4], m_flags[RSP_VCC].s[5], m_flags[RSP_VCC].s[6], m_flags[RSP_VCC].s[7]);
4192		printf("vcc_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCC].s[8], m_flags[RSP_VCC].s[9], m_flags[RSP_VCC].s[10], m_flags[RSP_VCC].s[11], m_flags[RSP_VCC].s[12], m_flags[RSP_VCC].s[13], m_flags[RSP_VCC].s[14], m_flags[RSP_VCC].s[15]);
4193		printf("vco_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCO].s[0], m_flags[RSP_VCO].s[1], m_flags[RSP_VCO].s[2], m_flags[RSP_VCO].s[3], m_flags[RSP_VCO].s[4], m_flags[RSP_VCO].s[5], m_flags[RSP_VCO].s[6], m_flags[RSP_VCO].s[7]);
4194		printf("vco_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCO].s[8], m_flags[RSP_VCO].s[9], m_flags[RSP_VCO].s[10], m_flags[RSP_VCO].s[11], m_flags[RSP_VCO].s[12], m_flags[RSP_VCO].s[13], m_flags[RSP_VCO].s[14], m_flags[RSP_VCO].s[15]);
4195		printf("vce: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCE].s[0], m_flags[RSP_VCE].s[1], m_flags[RSP_VCE].s[2], m_flags[RSP_VCE].s[3], m_flags[RSP_VCE].s[4], m_flags[RSP_VCE].s[5], m_flags[RSP_VCE].s[6], m_flags[RSP_VCE].s[7]);
	4188	printf("acc_h: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[0], m_acc.s[1], m_acc.s[2], m_acc.s[3], m_acc.s[4], m_acc.s[5], m_acc.s[6], m_acc.s[7]);
	4189	printf("acc_m: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[8], m_acc.s[9], m_acc.s[10], m_acc.s[11], m_acc.s[12], m_acc.s[13], m_acc.s[14], m_acc.s[15]);
	4190	printf("acc_l: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_acc.s[16], m_acc.s[17], m_acc.s[18], m_acc.s[19], m_acc.s[20], m_acc.s[21], m_acc.s[22], m_acc.s[23]);
	4191	printf("vcc_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCC].s[0], m_flags[RSP_VCC].s[1], m_flags[RSP_VCC].s[2], m_flags[RSP_VCC].s[3], m_flags[RSP_VCC].s[4], m_flags[RSP_VCC].s[5], m_flags[RSP_VCC].s[6], m_flags[RSP_VCC].s[7]);
	4192	printf("vcc_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCC].s[8], m_flags[RSP_VCC].s[9], m_flags[RSP_VCC].s[10], m_flags[RSP_VCC].s[11], m_flags[RSP_VCC].s[12], m_flags[RSP_VCC].s[13], m_flags[RSP_VCC].s[14], m_flags[RSP_VCC].s[15]);
	4193	printf("vco_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCO].s[0], m_flags[RSP_VCO].s[1], m_flags[RSP_VCO].s[2], m_flags[RSP_VCO].s[3], m_flags[RSP_VCO].s[4], m_flags[RSP_VCO].s[5], m_flags[RSP_VCO].s[6], m_flags[RSP_VCO].s[7]);
	4194	printf("vco_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCO].s[8], m_flags[RSP_VCO].s[9], m_flags[RSP_VCO].s[10], m_flags[RSP_VCO].s[11], m_flags[RSP_VCO].s[12], m_flags[RSP_VCO].s[13], m_flags[RSP_VCO].s[14], m_flags[RSP_VCO].s[15]);
	4195	printf("vce: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_flags[RSP_VCE].s[0], m_flags[RSP_VCE].s[1], m_flags[RSP_VCE].s[2], m_flags[RSP_VCE].s[3], m_flags[RSP_VCE].s[4], m_flags[RSP_VCE].s[5], m_flags[RSP_VCE].s[6], m_flags[RSP_VCE].s[7]);
4196	4196	#else
4197		printf("acc_h: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
4198		printf("acc_m: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
4199		printf("acc_l: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_L(0), ACCUM_L(1), ACCUM_L(2), ACCUM_L(3), ACCUM_L(4), ACCUM_L(5), ACCUM_L(6), ACCUM_L(7));
4200		printf("vcc_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[4][0], m_vflag[4][1], m_vflag[4][2], m_vflag[4][3], m_vflag[4][4], m_vflag[4][5], m_vflag[4][6], m_vflag[4][7]);
4201		printf("vcc_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[1][0], m_vflag[1][1], m_vflag[1][2], m_vflag[1][3], m_vflag[1][4], m_vflag[1][5], m_vflag[1][6], m_vflag[1][7]);
4202		printf("vco_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[3][0], m_vflag[3][1], m_vflag[3][2], m_vflag[3][3], m_vflag[3][4], m_vflag[3][5], m_vflag[3][6], m_vflag[3][7]);
4203		printf("vco_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[0][0], m_vflag[0][1], m_vflag[0][2], m_vflag[0][3], m_vflag[0][4], m_vflag[0][5], m_vflag[0][6], m_vflag[0][7]);
4204		printf("vce: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[2][0], m_vflag[2][1], m_vflag[2][2], m_vflag[2][3], m_vflag[2][4], m_vflag[2][5], m_vflag[2][6], m_vflag[2][7]);
	4197	printf("acc_h: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
	4198	printf("acc_m: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
	4199	printf("acc_l: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", ACCUM_L(0), ACCUM_L(1), ACCUM_L(2), ACCUM_L(3), ACCUM_L(4), ACCUM_L(5), ACCUM_L(6), ACCUM_L(7));
	4200	printf("vcc_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[4][0], m_vflag[4][1], m_vflag[4][2], m_vflag[4][3], m_vflag[4][4], m_vflag[4][5], m_vflag[4][6], m_vflag[4][7]);
	4201	printf("vcc_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[1][0], m_vflag[1][1], m_vflag[1][2], m_vflag[1][3], m_vflag[1][4], m_vflag[1][5], m_vflag[1][6], m_vflag[1][7]);
	4202	printf("vco_hi: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[3][0], m_vflag[3][1], m_vflag[3][2], m_vflag[3][3], m_vflag[3][4], m_vflag[3][5], m_vflag[3][6], m_vflag[3][7]);
	4203	printf("vco_lo: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[0][0], m_vflag[0][1], m_vflag[0][2], m_vflag[0][3], m_vflag[0][4], m_vflag[0][5], m_vflag[0][6], m_vflag[0][7]);
	4204	printf("vce: %04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\|%04x\n", m_vflag[2][0], m_vflag[2][1], m_vflag[2][2], m_vflag[2][3], m_vflag[2][4], m_vflag[2][5], m_vflag[2][6], m_vflag[2][7]);
4205	4205	#endif
4206	4206	}
4207	4207
4208	4208	void rsp_cop2::dump_dmem()
4209	4209	{
4210		UINT8* dmem = m_rsp.get_dmem();
4211		printf("\n");
4212		for (int i = 0; i < 0x1000; i += 32)
4213		{
4214		printf("%04x: ", i);
4215		for (int j = 0; j < 32; j++)
4216		{
4217		printf("%02x ", dmem[i + j]);
4218		}
4219		printf("\n");
4220		}
4221		printf("\n");
4222		}
		No newline at end of file
	4210	UINT8* dmem = m_rsp.get_dmem();
	4211	printf("\n");
	4212	for (int i = 0; i < 0x1000; i += 32)
	4213	{
	4214	printf("%04x: ", i);
	4215	for (int j = 0; j < 32; j++)
	4216	{
	4217	printf("%02x ", dmem[i + j]);
	4218	}
	4219	printf("\n");
	4220	}
	4221	printf("\n");
	4222	}

trunk/src/emu/cpu/rsp/rspcp2.h
r248551	r248552
17	17	#include "rsp.h"
18	18	#include "rspdiv.h"
19	19
20		#define SIMD_OFF (1)
	20	#define SIMD_OFF (1)
21	21
22	22	#if (defined(__SSE2__) \|\| defined(__SSE3__) \|\| defined(__SSSE3__) \|\| defined(__SSE4_1__) \|\| defined(__SSE4_2__))
23		#define SSE_AVAILABLE (1)
	23	#define SSE_AVAILABLE (1)
24	24	#else
25		#define SSE_AVAILABLE (0)
	25	#define SSE_AVAILABLE (0)
26	26	#endif
27	27
28	28	#if (SSE_AVAILABLE \|\| defined(_MSC_VER)) && defined(PTR64) && !SIMD_OFF
29		#define USE_SIMD (1)
	29	#define USE_SIMD (1)
30	30	#else
31		#define USE_SIMD (0)
	31	#define USE_SIMD (0)
32	32	#endif
33	33
34	34	#if USE_SIMD
r248551	r248552
167	167	void log_instruction_execution();
168	168	virtual void cfunc_unimplemented_opcode() { }
169	169
170		void dump(UINT32 op);
171		void dump_dmem();
	170	void dump(UINT32 op);
	171	void dump_dmem();
172	172
173	173	protected:
174	174	virtual int generate_vector_opcode(drcuml_block block, rsp_device::compiler_state compiler, const opcode_desc *desc) { return TRUE; }
r248551	r248552
342	342
343	343	static inline INT16 get_flags(const UINT16 *flags)
344	344	{
345		return _mm_movemask_epi8(_mm_packs_epi16(_mm_load_si128((rsp_vec_t) (flags + (sizeof(rsp_vec_t) >> 1))), _mm_load_si128((rsp_vec_t) flags)));
	345	return _mm_movemask_epi8(_mm_packs_epi16(_mm_load_si128((rsp_vec_t) (flags + (sizeof(rsp_vec_t) >> 1))), _mm_load_si128((rsp_vec_t) flags)));
346	346	}
347	347
348	348	static inline rsp_vec_t vec_zero()
r248551	r248552
389	389	void handle_swc2(UINT32 op);
390	390	void handle_vector_ops(UINT32 op);
391	391
392		UINT32 m_div_in;
393		UINT32 m_div_out;
	392	UINT32 m_div_in;
	393	UINT32 m_div_out;
394	394	};
395	395
396	396	#endif /* __RSPCP2_H__ */

trunk/src/emu/cpu/rsp/vadd.h
r248551	r248552
14	14	minimum = _mm_subs_epi16(minimum, carry);
15	15	return _mm_adds_epi16(minimum, maximum);
16	16	}
17

trunk/src/emu/cpu/rsp/vcl.h
r248551	r248552
46	46	ge = _mm_or_si128(ge_eq, ge);
47	47	#endif
48	48
49		// Mux the result based on the value of sign.
	49	// Mux the result based on the value of sign.
50	50	#if (defined(__SSE4_1__) \|\| defined(_MSC_VER))
51	51	rsp_vec_t mux_mask = _mm_blendv_epi8(ge, le, sign);
52	52	#else

trunk/src/emu/cpu/rsp/vmudh.h
r248551	r248552
8	8
9	9	return sclamp_acc_to_mid(acc_md, acc_hi);
10	10	}
11

trunk/src/emu/cpu/rsp/vmulh.h
r248551	r248552
28	28
29	29	return sclamp_acc_to_mid(acc_md, acc_hi);
30	30	}
31

trunk/src/emu/cpu/rsp/vrcpsq.h
r248551	r248552
26	26	}
27	27	else if (input == -32768)
28	28	{
29		result = 0xffff0000;
	29	result = 0xffff0000;
30	30	}
31	31	else // Main case: compute the reciprocal.
32	32	{

trunk/src/emu/cpu/rsp/vrsq.h
r248551	r248552
26	26	}
27	27	else if (input == -32768)
28	28	{
29		result = 0xffff0000;
	29	result = 0xffff0000;
30	30	}
31	31	else // Main case: compute the reciprocal.
32	32	{

trunk/src/emu/cpu/sh2/sh2.c
r248551	r248552
143	143
144	144	static ADDRESS_MAP_START( sh7604_map, AS_PROGRAM, 32, sh2_device )
145	145	AM_RANGE(0x40000000, 0xbfffffff) AM_READ(sh2_internal_a5)
146		/*!
	146	/*!
147	147	@todo: cps3boot breaks with this enabled. Needs customization ...
148	148	*/
149		// AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM // cache data array
150		// AM_RANGE(0xffffff88, 0xffffff8b) AM_READWRITE(dma_dtcr0_r,dma_dtcr0_w)
	149	// AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM // cache data array
	150	// AM_RANGE(0xffffff88, 0xffffff8b) AM_READWRITE(dma_dtcr0_r,dma_dtcr0_w)
151	151	AM_RANGE(0xe0000000, 0xe00001ff) AM_MIRROR(0x1ffffe00) AM_READWRITE(sh7604_r, sh7604_w)
152	152	ADDRESS_MAP_END
153	153
r248551	r248552
159	159	AM_RANGE(0x05ffff48, 0x05ffff4b) AM_READWRITE16(dma_tcr0_r, dma_tcr0_w,0x0000ffff)
160	160	AM_RANGE(0x05ffff4c, 0x05ffff4f) AM_READWRITE16(dma_chcr0_r, dma_chcr0_w, 0x0000ffff)
161	161	// fall-back
162		AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7021_r,sh7021_w,0xffffffff) // SH-7032H internal i/o
163		// AM_RANGE(0x07000000, 0x070003ff) AM_RAM AM_SHARE("oram")// on-chip RAM, actually at 0xf000000 (1 kb)
164		// AM_RANGE(0x0f000000, 0x0f0003ff) AM_RAM AM_SHARE("oram")// on-chip RAM, actually at 0xf000000 (1 kb)
	162	AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7021_r,sh7021_w,0xffffffff) // SH-7032H internal i/o
	163	// AM_RANGE(0x07000000, 0x070003ff) AM_RAM AM_SHARE("oram")// on-chip RAM, actually at 0xf000000 (1 kb)
	164	// AM_RANGE(0x0f000000, 0x0f0003ff) AM_RAM AM_SHARE("oram")// on-chip RAM, actually at 0xf000000 (1 kb)
165	165	ADDRESS_MAP_END
166	166
167	167	static ADDRESS_MAP_START( sh7032_map, AS_PROGRAM, 32, sh1_device )
168	168	// fall-back
169		AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7032_r,sh7032_w,0xffffffff) // SH-7032H internal i/o
	169	AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7032_r,sh7032_w,0xffffffff) // SH-7032H internal i/o
170	170	ADDRESS_MAP_END
171	171
172	172	sh2_device::sh2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
r248551	r248552
300	300	m_program->write_byte(A & AM,V);
301	301	return;
302	302	}
303
	303
304	304	m_program->write_byte(A,V);
305	305	}
306	306
r248551	r248552
311	311	m_program->write_word(A & AM,V);
312	312	return;
313	313	}
314
	314
315	315	m_program->write_word(A,V);
316	316	}
317	317
r248551	r248552
322	322	m_program->write_dword(A & AM,V);
323	323	return;
324	324	}
325
	325
326	326	/* 0x20000000 no Cache */
327	327	/* 0x00000000 read thru Cache if CE bit is 1 */
328	328	m_program->write_dword(A,V);

trunk/src/emu/cpu/sh2/sh2.h
r248551	r248552
513	513	DECLARE_READ16_MEMBER(sh7021_r);
514	514	DECLARE_WRITE16_MEMBER(sh7021_w);
515	515	void sh7032_dma_exec(int ch);
516
	516
517	517	private:
518	518	UINT16 m_sh7021_regs[0x200];
519	519	struct
520	520	{
521		UINT32 sar; /*< Source Address Register /
522		UINT32 dar; /*< Destination Address Register /
523		UINT16 tcr; /*< Transfer Count Register /
524		UINT16 chcr; /*< Channel Control Register /
	521	UINT32 sar; /*< Source Address Register /
	522	UINT32 dar; /*< Destination Address Register /
	523	UINT16 tcr; /*< Transfer Count Register /
	524	UINT16 chcr; /*< Channel Control Register /
525	525	} m_dma[4];
526		UINT16 m_dmaor; /*< DMA Operation Register (status flags) /
	526	UINT16 m_dmaor; /*< DMA Operation Register (status flags) /
527	527
528	528	};
529	529

trunk/src/emu/cpu/sh2/sh2comn.c
r248551	r248552
899	899	void sh2a_device::sh7032_dma_exec(int ch)
900	900	{
901	901	const short dma_word_size[4] = { 0, +1, -1, 0 };
902		UINT8 rs = (m_dma[ch].chcr >> 8) & 0xf; /*< Resource Select bits /
	902	UINT8 rs = (m_dma[ch].chcr >> 8) & 0xf; /*< Resource Select bits /
903	903	if(rs != 0xc) // Auto-Request
904	904	{
905	905	logerror("Warning: SH7032 DMA enables non auto-request transfer\n");
r248551	r248552
911	911	return;
912	912
913	913	printf("%08x %08x %04x\n",m_dma[ch].sar,m_dma[ch].dar,m_dma[ch].chcr);
914		UINT8 dm = (m_dma[ch].chcr >> 14) & 3; /*< Destination Address Mode bits /
915		UINT8 sm = (m_dma[ch].chcr >> 12) & 3; /*< Source Address Mode bits /
916		bool ts = (m_dma[ch].chcr & 8); /*< Transfer Size bit /
	914	UINT8 dm = (m_dma[ch].chcr >> 14) & 3; /*< Destination Address Mode bits /
	915	UINT8 sm = (m_dma[ch].chcr >> 12) & 3; /*< Source Address Mode bits /
	916	bool ts = (m_dma[ch].chcr & 8); /*< Transfer Size bit /
917	917	int src_word_size = dma_word_size[sm] * ((ts == true) ? 2 : 1);
918	918	int dst_word_size = dma_word_size[dm] * ((ts == true) ? 2 : 1);
919	919	UINT32 src_addr = m_dma[ch].sar;
r248551	r248552
1025	1025	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
1026	1026	#pragma GCC diagnostic pop
1027	1027	#endif
1028

trunk/src/emu/cpu/sm510/sm510.c
r248551	r248552
6	6	- SM510: 2.7Kx8 ROM, 128x4 RAM(32x4 for LCD)
7	7	- SM511: 4Kx8 ROM, 128x4 RAM(32x4 for LCD), melody controller
8	8	- SM512: 4Kx8 ROM, 128x4 RAM(48x4 for LCD), melody controller
9
	9
10	10	Other chips that may be in the same family, investigate more when one of
11	11	them needs to get emulated: SM500, SM530/31, SM4A, SM3903, ..
12	12
13	13	References:
14	14	- 1990 Sharp Microcomputers Data Book
15	15	- 1996 Sharp Microcomputer Databook
16
	16
17	17	TODO:
18	18	- proper support for LFSR program counter in debugger
19	19	- callback for lcd screen as MAME bitmap (when needed)
r248551	r248552
146	146	m_op = m_prev_op = 0;
147	147	do_branch(3, 7, 0);
148	148	m_prev_pc = m_pc;
149
	149
150	150	// lcd is on (Bp on, BC off, bs(y) off)
151	151	m_bp = true;
152	152	m_bc = false;
153	153	m_y = 0;
154
	154
155	155	m_r = 0;
156	156	m_write_r(0, 0, 0xff);
157	157	m_melody_rd &= ~1;
r248551	r248552
168	168	// output 0 if lcd blackpate/bleeder is off, or in case row doesn't exist
169	169	if (ram == NULL \|\| m_bc \|\| !m_bp)
170	170	return 0;
171
	171
172	172	UINT16 rowdata = 0;
173	173	for (int i = 0; i < 0x10; i++)
174	174	rowdata \|= (ram[i] >> column & 1) << i;
175
	175
176	176	return rowdata;
177	177	}
178	178
r248551	r248552
185	185	m_write_sega(h \| SM510_PORT_SEGA, get_lcd_row(h, m_lcd_ram_a), 0xffff);
186	186	m_write_segb(h \| SM510_PORT_SEGB, get_lcd_row(h, m_lcd_ram_b), 0xffff);
187	187	m_write_segc(h \| SM510_PORT_SEGC, get_lcd_row(h, m_lcd_ram_c), 0xffff);
188
	188
189	189	// bs output from L/X and Y regs
190	190	UINT8 bs = (m_l >> h & 1) \| ((m_x*2) >> h & 2);
191	191	m_write_segbs(h \| SM510_PORT_SEGBS, (m_bc \|\| !m_bp) ? 0 : bs, 0xffff);
192	192	}
193
	193
194	194	// schedule next timeout
195	195	m_lcd_timer->adjust(attotime::from_ticks(0x200, unscaled_clock()));
196	196	}
r248551	r248552
222	222	0, 0, 8, 8, 9, 9, 10,10,11,12,12,13,14,15, 82, 82,
223	223	0, 0, 8, 9, 9, 10,10,11,11,12,13,14,14,15, 82, 92
224	224	};
225
	225
226	226	UINT8 cmd = m_melody_rom[m_melody_address] & 0x3f;
227	227	UINT8 out = 0;
228
	228
229	229	// clock duty cycle if tone is active
230	230	if ((cmd & 0xf) > 1)
231	231	{
r248551	r248552
245	245	// rest tell signal
246	246	m_melody_rd \|= 2;
247	247	}
248
	248
249	249	// clock time base on F8(d7)
250	250	if ((m_div & 0x7f) == 0)
251	251	{
r248551	r248552
255	255	if (m_melody_step_count == 0)
256	256	m_melody_address++;
257	257	}
258
	258
259	259	// output to R pin
260	260	if (out != m_r)
261	261	{
r248551	r248552
293	293	// after waking up, but we leave it unchanged
294	294	m_halt = false;
295	295	do_branch(1, 0, 0);
296
	296
297	297	standard_irq_callback(0);
298	298	return true;
299	299	}
r248551	r248552
305	305	{
306	306	if (line != SM510_INPUT_LINE_K)
307	307	return;
308
	308
309	309	// set K input lines active state
310	310	m_k_active = (state != 0);
311	311	}
r248551	r248552
317	317	// 1S signal on overflow(falling edge of f1)
318	318	if (m_div == 0)
319	319	m_1s = true;
320
	320
321	321	clock_melody();
322	322	}
323	323

trunk/src/emu/cpu/sm510/sm510.h
r248551	r248552
134	134	int m_stack_levels;
135	135	UINT16 m_stack[2];
136	136	int m_icount;
137
	137
138	138	UINT8 m_acc;
139	139	UINT8 m_bl;
140	140	UINT8 m_bm;
r248551	r248552
177	177	bool wake_me_up();
178	178	void init_divider();
179	179	TIMER_CALLBACK_MEMBER(div_timer_cb);
180
	180
181	181	// other i/o handlers
182	182	devcb_read8 m_read_k;
183	183	devcb_read_line m_read_ba;
r248551	r248552
251	251
252	252	void op_rm();
253	253	void op_sm();
254
	254
255	255	void op_pre();
256	256	void op_sme();
257	257	void op_rme();
258	258	void op_tmel();
259
	259
260	260	void op_skip();
261	261	void op_cend();
262	262	void op_idiv();
r248551	r248552
274	274	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
275	275	virtual void execute_one();
276	276	virtual void get_opcode_param();
277
	277
278	278	virtual void update_w_latch() { m_write_s(0, m_w, 0xff); } // W is connected directly to S
279	279	};
280	280

trunk/src/emu/cpu/sm510/sm510d.c
r248551	r248552
103	103	param = oprom[s_next_pc[pc & 0x3f]];
104	104	len++;
105	105	}
106
	106
107	107	// extended opcode
108	108	bool is_extended = (instr == mEXT);
109	109	if (is_extended)
r248551	r248552
131	131	UINT16 address = (param << 4 & 0xc00) \| (mask << 6 & 0x3c0) \| (param & 0x03f);
132	132	dst += sprintf(dst, "$%03X", address);
133	133	}
134
	134
135	135	// show param offset
136	136	if (bits >= 8)
137	137	dst += sprintf(dst, " [$%03X]", pc + s_next_pc[pc & 0x3f]);
138	138	}
139
	139
140	140	return len \| s_flags[instr] \| DASMFLAG_SUPPORTED;
141	141	}
142	142
r248551	r248552
210	210	UINT8 ext[0x100];
211	211	memset(ext, 0, 0x100);
212	212	memcpy(ext + 0x30, sm511_extended, 0x10);
213
	213
214	214	return sm510_common_disasm(sm511_mnemonic, ext, buffer, pc, oprom, opram);
215	215	}

trunk/src/emu/cpu/sm510/sm510op.c
r248551	r248552
57	57	void sm510_base_device::op_lb()
58	58	{
59	59	// LB x: load BM/BL with 4-bit immediate value (partial)
60
	60
61	61	// SM510 WIP..
62	62	// bm and bl(low) are probably ok!
63	63	m_bm = (m_bm & 4) \| (m_op & 3);
64	64	m_bl = (m_op >> 2 & 3);
65
	65
66	66	// bl(high) is still unclear, official doc is confusing
67	67	UINT8 hi = 0;
68	68	switch (m_bl)

trunk/src/emu/cpu/sm510/sm511core.c
r248551	r248552
102	102	switch (m_op)
103	103	{
104	104	case 0x00: op_rot(); break;
105		// case 0x01: op_xxx(); break; // ?
	105	// case 0x01: op_xxx(); break; // ?
106	106	case 0x02: op_sbm(); break;
107	107	case 0x03: op_atpl(); break;
108	108	case 0x08: op_add(); break;
r248551	r248552
119	119	case 0x5a: op_ta0(); break;
120	120	case 0x5b: op_tabl(); break;
121	121	case 0x5c: op_atx(); break;
122		// case 0x5d: op_cend(); break;
	122	// case 0x5d: op_cend(); break;
123	123	case 0x5e: op_tal(); break;
124	124	case 0x5f: op_lbl(); break;
125	125
r248551	r248552
127	127	case 0x62: op_wr(); break;
128	128	case 0x63: op_ws(); break;
129	129	case 0x64: op_incb(); break;
130		// case 0x65: op_idiv(); break;
	130	// case 0x65: op_idiv(); break;
131	131	case 0x66: op_rc(); break;
132	132	case 0x67: op_sc(); break;
133	133	case 0x6c: op_decb(); break;
134	134	case 0x6d: op_ptw(); break;
135	135	case 0x6e: op_rtn0(); break;
136	136	case 0x6f: op_rtn1(); break;
137
	137
138	138	// extended opcodes
139	139	case 0x60:
140	140	m_op = m_op << 8 \| m_param;

trunk/src/emu/cpu/ucom4/ucom4.h
r248551	r248552
323	323	public:
324	324	upd650_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
325	325
326		protected:
	326	protected:
327	327	virtual UINT8 input_r(int index);
328	328	};
329	329

trunk/src/emu/cpu/ucom4/ucom4op.c
r248551	r248552
59	59	// bidirectional ports are 'push-pull', meaning it will output 0 when it's read
60	60	if ((index & 0xf) == NEC_UCOM4_PORTC \|\| (index & 0xf) == NEC_UCOM4_PORTD)
61	61	output_w(index, 0);
62
	62
63	63	return ucom4_cpu_device::input_r(index);
64	64	}
65	65

trunk/src/emu/machine/68230pit.c
r248551	r248552
1	1	// license:BSD-3-Clause
2		// copyright-holders:Joakim Larsson Edström
	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
4	4
5	5	Motorola MC68230 PI/T Parallell Interface and Timer
r248551	r248552
46	46	//-------------------------------------------------
47	47
48	48	pit68230_device::pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
49		: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__)
	49	: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__)
50	50	{
51	51	}
52	52
53	53	void pit68230_device::device_start()
54	54	{
55		printf("PIT68230 device started\n");
	55	printf("PIT68230 device started\n");
56	56	}
57	57
58	58	void pit68230_device::device_reset()
59	59	{
60		printf("PIT68230 device reseted\n");
61		m_pgcr = 0;
62		m_psrr = 0;
63		m_paddr = 0;
64		m_pbddr = 0;
65		m_pcddr = 0;
66		m_pacr = 0;
67		m_pbcr = 0;
68		m_padr = 0;
69		m_pbdr = 0;
70		m_psr = 0;
	60	printf("PIT68230 device reseted\n");
	61	m_pgcr = 0;
	62	m_psrr = 0;
	63	m_paddr = 0;
	64	m_pbddr = 0;
	65	m_pcddr = 0;
	66	m_pacr = 0;
	67	m_pbcr = 0;
	68	m_padr = 0;
	69	m_pbdr = 0;
	70	m_psr = 0;
71	71	}
72	72
73	73	WRITE8_MEMBER( pit68230_device::data_w )
74	74	{
75		printf("data_w: %04x -> ", data);
76		switch (offset)
77		{
78		case PIT_68230_PGCR:
79		printf("PGCR");
80		m_pgcr = data;
81		break;
82		case PIT_68230_PSRR:
83		printf("PSRR");
84		m_psrr = data;
85		break;
86		case PIT_68230_PADDR:
87		printf("PADDR");
88		m_paddr = data;
89		break;
90		case PIT_68230_PBDDR:
91		printf("PBDDR");
92		m_pbddr = data;
93		break;
94		case PIT_68230_PACR:
95		printf("PACR");
96		m_pacr = data;
97		break;
98		case PIT_68230_PBCR:
99		printf("PBCR");
100		m_pbcr = data;
101		break;
102		case PIT_68230_PADR:
103		printf("PADR");
104		m_padr = data;
105		break;
106		case PIT_68230_PSR:
107		printf("PSR");
108		m_padr = data;
109		break;
110		default:
111		printf("unhandled register %02x", offset);
112		}
113		printf("\n");
	75	printf("data_w: %04x -> ", data);
	76	switch (offset)
	77	{
	78	case PIT_68230_PGCR:
	79	printf("PGCR");
	80	m_pgcr = data;
	81	break;
	82	case PIT_68230_PSRR:
	83	printf("PSRR");
	84	m_psrr = data;
	85	break;
	86	case PIT_68230_PADDR:
	87	printf("PADDR");
	88	m_paddr = data;
	89	break;
	90	case PIT_68230_PBDDR:
	91	printf("PBDDR");
	92	m_pbddr = data;
	93	break;
	94	case PIT_68230_PACR:
	95	printf("PACR");
	96	m_pacr = data;
	97	break;
	98	case PIT_68230_PBCR:
	99	printf("PBCR");
	100	m_pbcr = data;
	101	break;
	102	case PIT_68230_PADR:
	103	printf("PADR");
	104	m_padr = data;
	105	break;
	106	case PIT_68230_PSR:
	107	printf("PSR");
	108	m_padr = data;
	109	break;
	110	default:
	111	printf("unhandled register %02x", offset);
	112	}
	113	printf("\n");
114	114	}
115	115
116	116	READ8_MEMBER( pit68230_device::data_r )
117	117	{
118		UINT8 data = 0;
	118	UINT8 data = 0;
119	119
120		printf("data_r: ");
121		switch (offset)
122		{
123		case PIT_68230_PGCR:
124		printf("PGCR");
125		data = m_pgcr;
126		break;
127		case PIT_68230_PSRR:
128		printf("PSRR");
129		data = m_psrr;
130		break;
131		case PIT_68230_PADDR:
132		printf("PADDR");
133		data = m_paddr;
134		break;
135		case PIT_68230_PBDDR:
136		printf("PBDDR");
137		data = m_pbddr;
138		break;
139		case PIT_68230_PACR:
140		printf("PACR");
141		data = m_pacr;
142		break;
143		case PIT_68230_PBCR:
144		printf("PBCR");
145		data = m_pbcr;
146		break;
147		case PIT_68230_PADR:
148		printf("PADR");
149		data = m_padr;
150		break;
151		case PIT_68230_PBDR:
152		/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
	120	printf("data_r: ");
	121	switch (offset)
	122	{
	123	case PIT_68230_PGCR:
	124	printf("PGCR");
	125	data = m_pgcr;
	126	break;
	127	case PIT_68230_PSRR:
	128	printf("PSRR");
	129	data = m_psrr;
	130	break;
	131	case PIT_68230_PADDR:
	132	printf("PADDR");
	133	data = m_paddr;
	134	break;
	135	case PIT_68230_PBDDR:
	136	printf("PBDDR");
	137	data = m_pbddr;
	138	break;
	139	case PIT_68230_PACR:
	140	printf("PACR");
	141	data = m_pacr;
	142	break;
	143	case PIT_68230_PBCR:
	144	printf("PBCR");
	145	data = m_pbcr;
	146	break;
	147	case PIT_68230_PADR:
	148	printf("PADR");
	149	data = m_padr;
	150	break;
	151	case PIT_68230_PBDR:
	152	/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
153	153	to and from port B pins. The port B data direction register determines whether each pin is an input (zero)
154		or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
	154	or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
155	155	reading or writing may affect the double-buffered handshake mechanism. The port B data register is not affected
156		by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
157		printf("PBDR");
158		data = m_pbdr;
159		// data = (m_pbdr & 0xfc) \| 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
160		break;
161		case PIT_68230_PSR:
162		printf("PSR");
163		data = m_psr;
164		// data = m_psr \| 1; // CPU-1 centronics interface expects status to be non zero
165		break;
166		default:
167		printf("unhandled register %02x", offset);
168		data = 0;
169		}
170		printf("\n");
	156	by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
	157	printf("PBDR");
	158	data = m_pbdr;
	159	// data = (m_pbdr & 0xfc) \| 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
	160	break;
	161	case PIT_68230_PSR:
	162	printf("PSR");
	163	data = m_psr;
	164	// data = m_psr \| 1; // CPU-1 centronics interface expects status to be non zero
	165	break;
	166	default:
	167	printf("unhandled register %02x", offset);
	168	data = 0;
	169	}
	170	printf("\n");
171	171
172		return data;
	172	return data;
173	173	}
174
175

trunk/src/emu/machine/68230pit.h
r248551	r248552
1	1	// license:BSD-3-Clause
2		// copyright-holders:Joakim Larsson Edström
	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
4	4
5	5	Motorola MC68230 PI/T Parallell Interface and Timer
r248551	r248552
56	56	virtual void device_reset();
57	57
58	58	private:
59		UINT8 m_pgcr; // Port General Control register
	59	UINT8 m_pgcr; // Port General Control register
60	60	UINT8 m_psrr; // Port Service Request register
61	61	UINT8 m_paddr; // Port A Data Direction register
62	62	UINT8 m_pbddr; // Port B Data Direction register

trunk/src/emu/machine/atapihle.c
r248551	r248552
246	246
247	247	case IDE_COMMAND_CHECK_POWER_MODE:
248	248	m_status = IDE_STATUS_DRDY;
249		m_sector_count = 0xff; // Power mode: 0x00 = Standby, 0x80 = Idle mode, 0xff = Active mode or Idle mode
	249	m_sector_count = 0xff; // Power mode: 0x00 = Standby, 0x80 = Idle mode, 0xff = Active mode or Idle mode
250	250	set_irq(ASSERT_LINE);
251	251	break;
252	252

trunk/src/emu/machine/nvram.c
r248551	r248552
179	179	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
180	180	#pragma GCC diagnostic pop
181	181	#endif
182

trunk/src/emu/machine/pci.c
r248551	r248552
905	905
906	906	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
907	907	#pragma GCC diagnostic pop
908		#endif
		No newline at end of file
	908	#endif

trunk/src/emu/machine/saturn.c
r248551	r248552
38	38	H counter value 0x0ec (236) -> 0xe0
39	39	H counter value 0x12c (300) -> 0x100
40	40	- Timer 1 seems to count backwards compared to Timer 0 from setting 0x6b onward.
41		- Yabause claims that if VDP2 DISP bit isn't enabled then vblank irqs (hblank too?)
	41	- Yabause claims that if VDP2 DISP bit isn't enabled then vblank irqs (hblank too?)
42	42	doesn't happen.
43	43
44	44	**************************************************************************************/

trunk/src/emu/machine/smpc.c
r248551	r248552
686	686	case 0x0a:
687	687	case 0x0b:
688	688	popmessage ("SMPC: NETLINK %s, contact MAMEdev",(data & 1) ? "off" : "on");
689		break; case 0x0d:
	689	break; case 0x0d:
690	690	if(LOG_SMPC) printf ("SMPC: System Reset\n");
691	691	smpc_system_reset();
692	692	break;
r248551	r248552
943	943	res\|= 0xc;
944	944	break;
945	945	}
946
	946
947	947	return res;
948	948	}
949	949

trunk/src/emu/machine/stvcd.c
r248551	r248552
866	866	if(cr4 == 0)
867	867	hirqreg \|= (CMOK);
868	868	else
869		hirqreg \|= (CMOK\|DRDY);
	869	hirqreg \|= (CMOK\|DRDY);
870	870	status_type = 1;
871	871	}
872	872	break;

trunk/src/emu/machine/tms6100.c
r248551	r248552
201	201	/* read bit at address */
202	202	/* if (m_variant == TMS6110_IS_M58819)
203	203	{
204		m_data = (m_rom[m_address >> 3] >> (7-(m_address & 0x07))) & 1;
	204	m_data = (m_rom[m_address >> 3] >> (7-(m_address & 0x07))) & 1;
205	205	}
206	206	else // m_variant == (TMS6110_IS_TMS6100 \|\| TMS6110_IS_TMS6125)
207	207	{
208		*/
	208	*/
209	209	m_data = (m_rom[m_address >> 3] >> (m_address & 0x07)) & 1;
210	210	/* } */
211	211	m_address++;

trunk/src/emu/machine/wd_fdc.h
r248551	r248552
179	179	void hlt_w(bool state);
180	180
181	181	bool enp_r();
182
	182
183	183	void index_callback(floppy_image_device *floppy, int state);
184	184
185	185	protected:

trunk/src/emu/mconfig.h
r248551	r248552
62	62	std::string m_perfect_cpu_quantum; // tag of CPU to use for "perfect" scheduling
63	63	INT32 m_watchdog_vblank_count; // number of VBLANKs until the watchdog kills us
64	64	attotime m_watchdog_time; // length of time until the watchdog kills us
65		bool m_force_no_drc; // whether or not to force DRC off
	65	bool m_force_no_drc; // whether or not to force DRC off
66	66
67	67	// other parameters
68	68	const char * m_default_layout; // default layout for this machine

trunk/src/emu/netlist/analog/nld_opamps.c
r248551	r248552
42	42
43	43	/*
44	44	* Type = 0: Impedance changer
45		* 1; Ideal opamp
46		* 2; opamp with first pole
47		* 3: opamp with first pole + output limit
48		* 4: opamp with input stage, first pole + output limit
	45	* 1; Ideal opamp
	46	* 2; opamp with first pole
	47	* 3: opamp with first pole + output limit
	48	* 4: opamp with input stage, first pole + output limit
49	49	*/
50	50
51	51	NETLIB_START(OPAMP)
r248551	r248552
141	141
142	142	/*
143	143	NETLIB_DEVICE_WITH_PARAMS(OPAMPx,
144		NETLIB_NAME(R) m_RP;
145		NETLIB_NAME(C) m_CP;
146		NETLIB_NAME(VCCS) m_G1;
147		NETLIB_NAME(VCVS) m_EBUF;
	144	NETLIB_NAME(R) m_RP;
	145	NETLIB_NAME(C) m_CP;
	146	NETLIB_NAME(VCCS) m_G1;
	147	NETLIB_NAME(VCVS) m_EBUF;
148	148
149		param_model_t m_model;
150		analog_input_t m_VH;
151		analog_input_t m_VL;
152		analog_input_t m_VREF;
	149	param_model_t m_model;
	150	analog_input_t m_VH;
	151	analog_input_t m_VL;
	152	analog_input_t m_VREF;
153	153	);
154	154	*/
155	155
156	156	NETLIB_NAMESPACE_DEVICES_END()
157

trunk/src/emu/netlist/devices/net_lib.c
r248551	r248552
72	72	ENTRY(VCCS, VCCS, "-")
73	73	ENTRY(CCCS, CCCS, "-")
74	74	ENTRY(LVCCS, LVCCS, "-")
75		ENTRY(VS, VS, "V")
	75	ENTRY(VS, VS, "V")
76	76	ENTRY(CS, CS, "I")
77	77	ENTRY(OPAMP, OPAMP, "MODEL")
78	78	ENTRY(dummy_input, DUMMY_INPUT, "-")
79	79	ENTRY(frontier, FRONTIER_DEV, "+I,G,Q") // not intended to be used directly
80		ENTRY(function, AFUNC, "N,FUNC") // only for macro devices - NO FEEDBACK loops
	80	ENTRY(function, AFUNC, "N,FUNC") // only for macro devices - NO FEEDBACK loops
81	81	ENTRY(QBJT_EB, QBJT_EB, "MODEL")
82	82	ENTRY(QBJT_switch, QBJT_SW, "MODEL")
83	83	ENTRY(logic_input, TTL_INPUT, "IN")

trunk/src/emu/netlist/devices/nld_log.h
r248551	r248552
21	21	#include "../nl_base.h"
22	22
23	23	#define LOG(_name, _I) \
24		NET_REGISTER_DEV(ÖPG, _name) \
	24	NET_REGISTER_DEV(??PG, _name) \
25	25	NET_CONNECT(_name, I, _I)
26	26
27	27	NETLIB_NAMESPACE_DEVICES_START()

trunk/src/emu/netlist/devices/nld_system.h
r248551	r248552
24	24
25	25	#define LOGIC_INPUT(_name, _v, _family) \
26	26	NET_REGISTER_DEV(LOGIC_INPUT, _name) \
27		PARAM(_name.IN, _v) \
	27	PARAM(_name.IN, _v) \
28	28	PARAM(_name.FAMILY, _family)
29	29
30	30	#define ANALOG_INPUT(_name, _v) \
r248551	r248552
70	70	#define PARAMETERS(_name) \
71	71	NET_REGISTER_DEV(PARAMETERS, _name)
72	72
73		#define AFUNC(_name, _N, _F) \
	73	#define AFUNC(_name, _N, _F) \
74	74	NET_REGISTER_DEV(AFUNC, _name) \
75		PARAM(_name.N, _N) \
	75	PARAM(_name.N, _N) \
76	76	PARAM(_name.FUNC, _F)
77	77
78	78	NETLIB_NAMESPACE_DEVICES_START()

trunk/src/emu/netlist/macro/nlm_cd4xxx.c
r248551	r248552
38	38	s2.A, /* A3 \|5 10\| Y5 */ s3.Q,
39	39	s2.B, /* Y3 \|6 9\| A4 */ s3.B,
40	40	VDD.I, /* GND \|7 8\| Y4 */ s3.A
41		/* +--------------+ */
	41	/* +--------------+ */
42	42	)
43	43
44	44	NETLIST_END()
r248551	r248552
74	74	s1.Q7, /* Q7 \|6 11\| RESET */ s1.RESET,
75	75	s1.Q4, /* Q4 \|7 10\| IP */ s1.IP,
76	76	s1.VSS, /* VSS \|8 9\| Q1 */ s1.Q1
77		/* +--------------+ */
	77	/* +--------------+ */
78	78	)
79	79	/*
80		* IP = (Input pulses)
	80	* IP = (Input pulses)
81	81	*/
82	82
83	83	NETLIST_END()
r248551	r248552
117	117	DIPPINS( /* +--------------+ */
118	118	A.R.1, /* INOUTA \|1 ++ 14\| VDD */ A.PS.VDD,
119	119	A.R.2, /* OUTINA \|2 13\| CONTROLA */ A.CTL,
120		B.R.1, /* OUTINB \|3 12\| CONTROLD */ D.CTL,
	120	B.R.1, /* OUTINB \|3 12\| CONTROLD */ D.CTL,
121	121	B.R.2, /* INOUTB \|4 4066 11\| INOUTD */ D.R.1,
122	122	B.CTL, /* CONTROLB \|5 10\| OUTIND */ D.R.2,
123	123	C.CTL, /* CONTROLC \|6 9\| OUTINC */ C.R.1,
124	124	A.PS.VSS, /* VSS \|7 8\| INOUTC */ C.R.2
125		/* +--------------+ */
	125	/* +--------------+ */
126	126	)
127	127	NETLIST_END()
128	128
r248551	r248552
143	143	DIPPINS( /* +--------------+ */
144	144	A.R.1, /* INOUTA \|1 ++ 14\| VDD */ A.PS.VDD,
145	145	A.R.2, /* OUTINA \|2 13\| CONTROLA */ A.CTL,
146		B.R.1, /* OUTINB \|3 12\| CONTROLD */ D.CTL,
	146	B.R.1, /* OUTINB \|3 12\| CONTROLD */ D.CTL,
147	147	B.R.2, /* INOUTB \|4 4016 11\| INOUTD */ D.R.1,
148	148	B.CTL, /* CONTROLB \|5 10\| OUTIND */ D.R.2,
149	149	C.CTL, /* CONTROLC \|6 9\| OUTINC */ C.R.1,
150	150	A.PS.VSS, /* VSS \|7 8\| INOUTC */ C.R.2
151		/* +--------------+ */
	151	/* +--------------+ */
152	152	)
153	153	NETLIST_END()
154	154

trunk/src/emu/netlist/macro/nlm_opamp.c
r248551	r248552
17	17	B.PLUS, /* \|5 10\| */ C.PLUS,
18	18	B.MINUS, /* \|6 9\| */ C.MINUS,
19	19	B.OUT, /* \|7 8\| */ C.OUT
20		/* +--------------+ */
	20	/* +--------------+ */
21	21	)
22	22	NET_C(A.GND, B.GND, C.GND, D.GND)
23	23	NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
r248551	r248552
33	33	A.MINUS, /* \|2 7\| */ B.OUT,
34	34	A.PLUS, /* \|3 6\| */ B.MINUS,
35	35	A.GND, /* \|4 5\| */ B.PLUS
36		/* +--------------+ */
	36	/* +--------------+ */
37	37	)
38	38	NET_C(A.GND, B.GND)
39	39	NET_C(A.VCC, B.VCC)

trunk/src/emu/netlist/macro/nlm_opamp.h
r248551	r248552
9	9	* Netlist Macros
10	10	* ---------------------------------------------------------------------------*/
11	11
12		#define MB3614_DIP(_name) \
	12	#define MB3614_DIP(_name) \
13	13	NET_REGISTER_DEV(MB3614_DIP, _name)
14	14
15		#define LM324_DIP(_name) \
	15	#define LM324_DIP(_name) \
16	16	NET_REGISTER_DEV(LM324_DIP, _name)
17	17
18		#define LM358_DIP(_name) \
	18	#define LM358_DIP(_name) \
19	19	NET_REGISTER_DEV(LM358_DIP, _name)
20	20
21	21	/* ----------------------------------------------------------------------------

trunk/src/emu/netlist/macro/nlm_other.c
r248551	r248552
6	6
7	7	/*
8	8	* MC14584B: Hex Schmitt Trigger
9		* ON Semiconductor
	9	* ON Semiconductor
10	10	*
11	11	* +--------------+
12	12	* A1 \|1 ++ 14\| VCC
r248551	r248552
39	39	s3.A, /* A3 \|5 10\| Y5 */ s5.Q,
40	40	s3.Q, /* Y3 \|6 9\| A4 */ s4.A,
41	41	GND.I, /* GND \|7 8\| Y4 */ s4.Q
42		/* +--------------+ */
	42	/* +--------------+ */
43	43	)
44	44	NETLIST_END()
45	45

trunk/src/emu/netlist/macro/nlm_other.h
r248551	r248552
9	9	* Netlist Macros
10	10	* ---------------------------------------------------------------------------*/
11	11
12		#define MC14584B_GATE(_name) \
	12	#define MC14584B_GATE(_name) \
13	13	NET_REGISTER_DEV(MC14584B_GATE, _name)
14	14
15		#define MC14584B_DIP(_name) \
	15	#define MC14584B_DIP(_name) \
16	16	NET_REGISTER_DEV(MC14584B_DIP, _name)
17	17
18	18

trunk/src/emu/netlist/macro/nlm_ttl74xx.c
r248551	r248552
6	6
7	7	/*
8	8	* DM7416: Hex Inverting Buffers with
9		* High Voltage Open-Collector Outputs
	9	* High Voltage Open-Collector Outputs
10	10	*
11	11	* +--------------+
12	12	* A1 \|1 ++ 14\| VCC
r248551	r248552
39	39	s3.A, /* A3 \|5 10\| Y5 */ s5.Q,
40	40	s3.Q, /* Y3 \|6 9\| A4 */ s4.A,
41	41	GND.I, /* GND \|7 8\| Y4 */ s4.Q
42		/* +--------------+ */
	42	/* +--------------+ */
43	43	)
44	44	NETLIST_END()
45	45

trunk/src/emu/netlist/macro/nlm_ttl74xx.h
r248551	r248552
9	9	* Netlist Macros
10	10	* ---------------------------------------------------------------------------*/
11	11
12		#define TTL_7416_GATE(_name) \
	12	#define TTL_7416_GATE(_name) \
13	13	NET_REGISTER_DEV(TTL_7416_GATE, _name)
14	14
15		#define TTL_7416_DIP(_name) \
	15	#define TTL_7416_DIP(_name) \
16	16	NET_REGISTER_DEV(TTL7416_DIP, _name)
17	17
18	18	/* ----------------------------------------------------------------------------

trunk/src/emu/netlist/nl_base.c
r248551	r248552
535	535
536	536	// FIXME: make this working again
537	537	//if (term.isType(terminal_t::INPUT) \|\| term.isType(terminal_t::TERMINAL))
538		// m_terminals.add(name);
	538	// m_terminals.add(name);
539	539	}
540	540
541	541	ATTR_COLD void device_t::register_terminal(const pstring &name, terminal_t &port)

trunk/src/emu/netlist/nl_base.h
r248551	r248552
241	241	, _priv)
242	242
243	243	#define NETLIB_LOGIC_FAMILY(_fam) \
244		virtual logic_family_desc_t *default_logic_family() \
	244	virtual logic_family_desc_t *default_logic_family() \
245	245	{ \
246	246	return netlist_family_ ## _fam; \
247	247	}
r248551	r248552
394	394	VCCS, // Voltage controlled current source
395	395	LVCCS, // Voltage controlled current source (Current limited)
396	396	CCCS, // Current controlled current source
397		VS, // Voltage Source
398		CS, // Current Source
	397	VS, // Voltage Source
	398	CS, // Current Source
399	399	GND // GND device
400	400	};
401	401

trunk/src/emu/netlist/nl_factory.c
r248551	r248552
34	34	}
35	35
36	36
37		factory_list_t::factory_list_t( setup_t &setup)
	37	factory_list_t::factory_list_t( setup_t &setup)
38	38	: m_setup(setup)
39	39	{
40	40	}

trunk/src/emu/netlist/nl_setup.h
r248551	r248552
58	58	setup.register_source(palloc(netlist::source_proc_t(# _name, &NETLIST_NAME(_name))));
59	59
60	60	#define LOCAL_LIB_ENTRY(_name) \
61		LOCAL_SOURCE(_name) \
	61	LOCAL_SOURCE(_name) \
62	62	setup.register_lib_entry(# _name);
63	63
64	64	#define INCLUDE(_name) \

trunk/src/emu/netlist/plib/palloc.h
r248551	r248552
79	79	pfree_raw(s);
80	80	}
81	81
82		#define palloc(T) new(ppool) T
	82	#define palloc(T) new(ppool) T
83	83	#define pfree(_ptr) pfree_t(_ptr)
84	84
85	85	#if 1
r248551	r248552
94	94
95	95	#define ATTR_ALIGN
96	96
97		#define palloc(T) global_alloc(T)
	97	#define palloc(T) global_alloc(T)
98	98	#define pfree(_ptr) global_free(_ptr)
99	99
100	100	#define palloc_array(T, N) global_alloc_array(T, N)

trunk/src/emu/netlist/plib/pconfig.h
r248551	r248552
40	40	//============================================================
41	41
42	42	// prevent implicit copying
43		#define P_PREVENT_COPYING(_name) \
	43	#define P_PREVENT_COPYING(_name) \
44	44	private: \
45	45	_name(const _name &); \
46	46	_name &operator=(const _name &);
r248551	r248552
234	234	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
235	235	#pragma GCC diagnostic pop
236	236	#endif
237

trunk/src/emu/netlist/plib/plists.h
r248551	r248552
657	657	#if 0
658	658	unsigned hash(const pstring &v) const
659	659	{
660		/* Fowler–Noll–Vo hash - FNV-1 */
	660	/* Fowler???Noll???Vo hash - FNV-1 */
661	661	const char *string = v.cstr();
662	662	unsigned result = 2166136261;
663	663	for (UINT8 c = string++; c != 0; c = string++)
r248551	r248552
671	671	/* jenkins one at a time algo */
672	672	unsigned result = 0;
673	673	const char *string = v.cstr();
674		while (*string)
675		{
676		result += *string;
677		string++;
678		result += (result << 10);
679		result ^= (result >> 6);
680		}
681		result += (result << 3);
682		result ^= (result >> 11);
683		result += (result << 15);
684		return result;
	674	while (*string)
	675	{
	676	result += *string;
	677	string++;
	678	result += (result << 10);
	679	result ^= (result >> 6);
	680	}
	681	result += (result << 3);
	682	result ^= (result >> 11);
	683	result += (result << 15);
	684	return result;
685	685	}
686	686	#endif
687	687	#endif

trunk/src/emu/netlist/plib/pstate.c
r248551	r248552
75	75	m_save.add(p);
76	76	state.register_state(*this, stname);
77	77	}
78

trunk/src/emu/netlist/solver/mat_cr.h
r248551	r248552
92	92	*
93	93	* ==> LUx = r
94	94	*
95		* ==> Ux = L⁻¹r = w
	95	* ==> Ux = L?????r = w
96	96	*
97	97	* ==> r = Lw
98	98	*

trunk/src/emu/netlist/solver/vector_base.h
r248551	r248552
42	42	}
43	43	inline double vecmult (const std::size_t n, const double * RESTRICT a1, const double * RESTRICT a2 )
44	44	{
45
46	45	double value = 0.0;
47	46	for ( std::size_t i = 0; i < n; i++ )
48	47	value = value + a1[i] * a2[i];

trunk/src/emu/netlist/tools/nl_convert.c
r248551	r248552
188	188	{"M", "CAP_M(%g)", 1.0e-3 },
189	189	{"u", "CAP_U(%g)", 1.0e-6 }, /* eagle */
190	190	{"U", "CAP_U(%g)", 1.0e-6 },
191		{"μ", "CAP_U(%g)", 1.0e-6 },
	191	{"??", "CAP_U(%g)", 1.0e-6 },
192	192	{"N", "CAP_N(%g)", 1.0e-9 },
193	193	{"P", "CAP_P(%g)", 1.0e-12},
194	194	{"F", "%ge-15", 1.0e-15},

trunk/src/emu/schedule.c
r248551	r248552
993	993	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
994	994	#pragma GCC diagnostic pop
995	995	#endif
996

trunk/src/emu/screen.h
r248551	r248552
355	355
356	356	/*!
357	357	@brief Configures screen parameters for the given screen.
358
	358
359	359	@param _pixclock Pixel Clock frequency value
360	360	@param _htotal Total number of horizontal pixels, including hblank period.
361	361	@param _hbend Horizontal pixel position for HBlank end event, also first pixel where screen rectangle is visible.
r248551	r248552
369	369
370	370	/*!
371	371	@brief Sets the number of Frames Per Second for this screen
372
	372
373	373	@param _rate FPS number
374	374	@deprecated Please use MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
375	375	*/
r248551	r248552
378	378
379	379	/*!
380	380	@brief Sets the vblank time of the given screen
381
	381
382	382	@param _time Time parameter, in attotime value\
383	383	@deprecated Please use MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
384	384	*/
r248551	r248552
387	387
388	388	/*!
389	389	@brief Sets total screen size, including H/V-Blanks
390
	390
391	391	@param _width Screen horizontal size
392	392	@param _height Screen vertical size
393	393	@deprecated Please use MCFG_SCREEN_RAW_PARAMS instead. Gives imprecise timings.
r248551	r248552
397	397
398	398	/*!
399	399	@brief Sets screen visible area
400
	400
401	401	@param _minx Screen left border
402	402	@param _maxx Screen right border, must be in N-1 format
403	403	@param _miny Screen top border

trunk/src/emu/sound/c140.c
r248551	r248552
134	134	/* allocate a pair of buffers to mix into - 1 second's worth should be more than enough */
135	135	m_mixer_buffer_left = auto_alloc_array(machine(), INT16, 2 * m_sample_rate);
136	136	m_mixer_buffer_right = m_mixer_buffer_left + m_sample_rate;
137
	137
138	138	save_item(NAME(m_REG));
139
	139
140	140	for (int i = 0; i < C140_MAX_VOICE; i++)
141		{
	141	{
142	142	save_item(NAME(m_voi[i].ptoffset), i);
143	143	save_item(NAME(m_voi[i].pos), i);
144	144	save_item(NAME(m_voi[i].key), i);

trunk/src/emu/sound/discrete.c
r248551	r248552
1146	1146	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
1147	1147	#pragma GCC diagnostic pop
1148	1148	#endif
1149

trunk/src/emu/sound/scsp.c
r248551	r248552
1051	1051	*/
1052	1052	logerror("SCSP: Reading from EXTS register %08x\n",addr);
1053	1053	if(addr == 0xee0)
1054		v = space.machine().device<cdda_device>("cdda")->get_channel_volume(0);
	1054	v = space.machine().device<cdda_device>("cdda")->get_channel_volume(0);
1055	1055	if(addr == 0xee2)
1056	1056	v = space.machine().device<cdda_device>("cdda")->get_channel_volume(1);
1057	1057	}

trunk/src/emu/sound/tms36xx.c
r248551	r248552
375	375	m_decay[0], m_decay[1], m_decay[2],
376	376	m_decay[3], m_decay[4], m_decay[5]));
377	377	LOG(("TMS36xx speed %d\n", m_speed));
378
	378
379	379	save_item(NAME(m_octave));
380	380	save_item(NAME(m_tune_counter));
381	381	save_item(NAME(m_note_counter));

trunk/src/emu/sound/ymf278b.c
r248551	r248552
1011	1011	// Register state for saving
1012	1012	register_save_state();
1013	1013
1014		// YMF262 related
	1014	// YMF262 related
1015	1015
1016	1016	/* stream system initialize */
1017	1017	int ymf262_clock = clock() / (19/8.0);

trunk/src/emu/video/hd44780.h
r248551	r248552
70	70	{
71	71	CHARSET_HD44780_A00,
72	72	CHARSET_KS0066_F05 /*,
73		CHARSET_HD44780_A01,
74		CHARSET_HD44780_A02,
75		CHARSET_KS0066_F00,
76		CHARSET_KS0066_F03,
77		CHARSET_KS0066_F04,
78		CHARSET_KS0066_F06,
79		CHARSET_KS0066_F59
80		*/
	73	CHARSET_HD44780_A01,
	74	CHARSET_HD44780_A02,
	75	CHARSET_KS0066_F00,
	76	CHARSET_KS0066_F03,
	77	CHARSET_KS0066_F04,
	78	CHARSET_KS0066_F06,
	79	CHARSET_KS0066_F59
	80	*/
81	81	};
82	82
83	83	void set_charset_type(int type);

trunk/src/emu/video/i82730.c
r248551	r248552
15	15	// CONSTANTS
16	16	//**************************************************************************
17	17
18		#define VERBOSE 1
19		#define VERBOSE_COMMANDS 1
20		#define VERBOSE_DATASTREAM 0
	18	#define VERBOSE 1
	19	#define VERBOSE_COMMANDS 1
	20	#define VERBOSE_DATASTREAM 0
21	21
22	22
23	23	//**************************************************************************

trunk/src/emu/video/i82730.h
r248551	r248552
35	35	// TYPE DEFINITIONS
36	36	//**************************************************************************
37	37
38		typedef device_delegate<void (bitmap_rgb32 &bitmap, UINT16 *data, UINT8 lc, UINT16 y, int x_count)> i82730_update_row_delegate;
	38	typedef device_delegate<void (bitmap_rgb32 &bitmap, UINT16 *data, UINT8 lc, UINT16 y, int x_count)> i82730_update_row_delegate;
39	39
40		#define I82730_UPDATE_ROW(name) \
	40	#define I82730_UPDATE_ROW(name) \
41	41	void name(bitmap_rgb32 &bitmap, UINT16 *data, UINT8 lc, UINT16 y, int x_count)
42	42
43	43

trunk/src/emu/video/mb_vcu.c
r248551	r248552
191	191	3, resistances_gb, m_weights_b, 3600, 0,
192	192	2, resistances_r, m_weights_r, 3600, 0);
193	193	}
194
	194
195	195	save_item(NAME(m_status));
196	196	save_pointer(NAME(m_ram), 0x800);
197	197	save_pointer(NAME(m_palram), 0x100);

trunk/src/emu/video/rgbsse.h
r248551	r248552
349	349	add(other);
350	350	clamp_to_uint8();
351	351	}
352
	352
353	353	inline void scale_add_and_clamp(const rgbaint_t& scale, const rgbaint_t& other)
354	354	{
355	355	mul(scale);
r248551	r248552
362	362	{
363	363	rgbaint_t color2(other);
364	364	color2.mul(scale2);
365
	365
366	366	mul(scale);
367	367	add(color2);
368	368	sra_imm(8);

trunk/src/emu/video/vooddefs.h
r248551	r248552
3209	3209	INT32 smax, tmax; \
3210	3210	UINT32 texbase; \
3211	3211	rgb_union c_local; \
3212		\
	3212	\
3213	3213	/* determine the S/T/LOD values for this texture */ \
3214	3214	if (TEXMODE_ENABLE_PERSPECTIVE(TEXMODE)) \
3215	3215	{ \
r248551	r248552
4743	4743	double recip = double(1ULL<<(47-39))/valueC;
4744	4744	double resAD = valueA * recip;
4745	4745	double resBD = valueB * recip;
4746		log = new_log2(recip);
4747		log += 56<<8;
4748		resA = resAD;
4749		resB = resBD;
	4746	log = new_log2(recip);
	4747	log += 56<<8;
	4748	resA = resAD;
	4749	resB = resBD;
4750	4750	}
4751	4751
4752	4752

trunk/src/mame/arcade.lst
r248551	r248552
44	44	maketrax // (c) 1981 Williams, high score table says KRL (fur Kural)
45	45	maketrxb // (c) 1981 [Kural] (Williams license)
46	46	korosuke // (c) 1981 Kural Electric
47		crushrlf // bootleg
	47	crushrlf // bootleg
48	48	mbrush // 1981 bootleg
49	49	paintrlr // 1981 bootleg
50	50	crushs // 1981 bootleg
r248551	r248552
339	339	scobra // GX316 (c) 1981 Konami
340	340	scobras // GX316 (c) 1981 Stern
341	341	scobrase // GX316 (c) 1981 Sega
342		scobrae // GX316 (c) 1981 Stern
	342	scobrae // GX316 (c) 1981 Stern
343	343	scobrab // GX316 (c) 1981 Karateco (bootleg?)
344	344	suprheli // bootleg
345	345	stratgyx // GX306 (c) 1981 Konami
r248551	r248552
684	684	vautour // bootleg (Jeutel)
685	685	falconz // bootleg
686	686	vautourz // bootleg
687		vautourza // bootleg (Jeutal)
	687	vautourza // bootleg (Jeutal)
688	688	griffon // bootleg (Videotron)
689	689	nextfase // bootleg
690	690	phoenixs // bootleg (Sonic)
691		phoenixass // bootleg (Assa)
	691	phoenixass // bootleg (Assa)
692	692	avefenix // bootleg (Video Game)
693	693	avefenixrf // bootleg (Recreativos Franco)
694		avefenixl // bootleg (Laguna)
	694	avefenixl // bootleg (Laguna)
695	695	pleiads // (c) 1981 Tehkan
696	696	pleiadsb2 // bootleg
697	697	pleiadbl // bootleg
r248551	r248552
1242	1242	marioj // (c) 1983 Nintendo
1243	1243	masao // bootleg
1244	1244	mariobl // bootleg
1245		mmagic // (c) 1979 Nintendo
	1245	mmagic // (c) 1979 Nintendo
1246	1246	dkong3abl //
1247	1247	pestplce // bootleg on donkey kong hw
1248	1248	spclforc // (c) 1985 Senko Industries (Magic Eletronics Inc. license)
r248551	r248552
3287	3287	rockmanj // 22/09/1995 (c) 1995 (Japan)
3288	3288	fcrash // bootleg of Final Fight
3289	3289	ffightbl // bootleg
3290		ffightbla // bootleg
	3290	ffightbla // bootleg
3291	3291	ganbare // 11/04/2000 (c) 2000 (Japan)
3292	3292
3293	3293
r248551	r248552
3454	3454	xmvsfr1 // 10/09/1996 (c) 1996 (Euro)
3455	3455	xmvsfu // 23/10/1996 (c) 1996 (USA)
3456	3456	xmvsfur1 // 04/10/1996 (c) 1996 (USA)
3457		xmvsfur2 // 10/09/1996 (c) 1996 (USA)
	3457	xmvsfur2 // 10/09/1996 (c) 1996 (USA)
3458	3458	xmvsfj // 04/10/1996 (c) 1996 (Japan)
3459	3459	xmvsfjr1 // 10/09/1996 (c) 1996 (Japan)
3460	3460	xmvsfjr2 // 09/09/1996 (c) 1996 (Japan)
r248551	r248552
4518	4518	turbo // (c) 1981 Sega
4519	4519	turboa // (c) 1981 Sega
4520	4520	turbob // (c) 1981 Sega
4521		turboc // (c) 1981 Sega
4522		turbod // (c) 1981 Sega
	4521	turboc // (c) 1981 Sega
	4522	turbod // (c) 1981 Sega
4523	4523	turbobl // bootleg
4524	4524	subroc3d // (c) 1982 Sega
4525	4525	buckrog // (c) 1982 Sega
r248551	r248552
4697	4697	passshtb // bootleg
4698	4698	shinoblb // (c) 1987 (but bootleg)
4699	4699	shinobld // (c) 1987 (but bootleg)
4700		shinoblda //
	4700	shinoblda //
4701	4701	tetrisbl // (c) 1988 (but bootleg)
4702	4702	beautyb // (c) 1991 AMT
4703	4703	iqpipe // (c) 1991 AMT
r248551	r248552
5772	5772	// 2006.09 Sega Network Taisen Mahjong MJ 3 Evolution (Rev A)
5773	5773	// 2006.10 Quest of D Oukoku no Syugosya Ver.3.00
5774	5774	// 2006.11 Quest of D Oukoku no Syugosya Ver.3.01
5775		mj3evo // 2007.06 Sega Network Taisen Mahjong MJ 3 Evolution (Rev B)
	5775	mj3evo // 2007.06 Sega Network Taisen Mahjong MJ 3 Evolution (Rev B)
5776	5776	// 2007.11 Quest of D The Battle Kingdom Ver.4.00
5777	5777	// 2008.01 Quest of D The Battle Kingdom Ver.4.00b
5778	5778	// 2008.02 Quest of D The Battle Kingdom Ver.4.00c
r248551	r248552
6031	6031	midresu // (c) 1989 Data East USA (US)
6032	6032	midresj // (c) 1989 Data East Corporation (Japan)
6033	6033	midresb // bootleg
6034		midresbj // bootleg
	6034	midresbj // bootleg
6035	6035	bouldash // (c) 1990 Data East Corporation (World)
6036	6036	bouldashj // (c) 1990 Data East Corporation (Japan)
6037	6037	// end of similar hardware
r248551	r248552
6481	6481	esckidsj // GX975 (c) 1991 (Japan)
6482	6482	vendetta // GX081 (c) 1991 (World)
6483	6483	vendettar // GX081 (c) 1991 (World)
6484		vendettaz // GX081 (c) 1991 (World)
	6484	vendettaz // GX081 (c) 1991 (World)
6485	6485	vendetta2p // GX081 (c) 1991 (World)
6486	6486	vendetta2peba // GX081 (c) 1991 (World)
6487	6487	vendetta2pu // GX081 (c) 1991 (Asia)
r248551	r248552
7139	7139	roadblstc // 136048 (c) 1986, 1987
7140	7140	roadblstcg // 136048 (c) 1986, 1987
7141	7141	roadblstc1 // 136048 (c) 1986, 1987
7142		roadblstgu // 136048 (c) 1986, 1987
	7142	roadblstgu // 136048 (c) 1986, 1987
7143	7143
7144	7144	// Atari System 2 games
7145	7145	// Paperboy
r248551	r248552
8282	8282	blitz // (c) 1997 Midway Games
8283	8283	blitz11 // (c) 1997 Midway Games
8284	8284	blitz99 // (c) 1998 Midway Games
8285		blitz99a // (c) 1998 Midway Games
	8285	blitz99a // (c) 1998 Midway Games
8286	8286	blitz2k // (c) 1999 Midway Games
8287	8287	hyprdriv // (c) 1998 Midway Games
8288	8288
r248551	r248552
8297	8297	warfa // (c) 1999 Atari Games
8298	8298	nbashowt // (c) 1998 Midway Games
8299	8299	nbanfl // (c) 1999 Midway Games
8300		nbagold // (c) 2000 Midway Games
	8300	nbagold // (c) 2000 Midway Games
8301	8301	gauntdl // (c) 1999 Midway Games
8302	8302	gauntdl24 // (c) 1999 Midway Games
8303	8303	cartfury // (c) 2000 Midway Games
r248551	r248552
8721	8721	stdragona // (c) 1989
8722	8722	rodland // (c) 1990
8723	8723	rodlandj // (c) 1990 (Japan)
8724		rittam // Prototype or hack of Rod-Land
	8724	rittam // Prototype or hack of Rod-Land
8725	8725	rodlandjb // bootleg
8726	8726	avspirit // (c) 1991
8727	8727	phantasm // (c) 1991 (Japan)
r248551	r248552
8801	8801	pspikesu // (c) 1991 Video System Co. (US)
8802	8802	svolly91 // (c) 1991 Video System Co. (Japan)
8803	8803	pspikesb // bootleg
8804		pspikesba // bootleg
	8804	pspikesba // bootleg
8805	8805	spikes91 // bootleg
8806	8806	spikes91b // bootleg
8807	8807	pspikesc // bootleg
8808	8808	karatblz // (c) 1991 Video System Co.
8809	8809	karatblzu // (c) 1991 Video System Co. (US)
8810	8810	karatblzj // (c) 1991 Video System / Tecmo (Japan)
8811		karatblzbl // bootleg
	8811	karatblzbl // bootleg
8812	8812	turbofrc // (c) 1991 Video System Co.
8813	8813	aerofgt // (c) 1992 Video System Co.
8814	8814	aerofgtb // (c) 1992 Video System Co.
r248551	r248552
8865	8865	dreamwld // (c) 2000 SemiCom
8866	8866	rolcrush // (c) 1999 Trust
8867	8867	cutefght // (c) 1998 SemiCom
8868		gaialast // (c) 1999 SemiCom
	8868	gaialast // (c) 1999 SemiCom
8869	8869
8870	8870	// SH2 board
8871	8871	s1945ii // (c) 1997
r248551	r248552
9686	9686	maya // (c) 1994 Promat
9687	9687	mayaa // (c) 1994 Promat
9688	9688	mayab // (c) 1994 Promat
9689		mayac // (c) 1994 Promat
	9689	mayac // (c) 1994 Promat
9690	9690	inca // (c) 199? ????
9691	9691	blktouch // (c) Yang Gi Co Ltd.
9692	9692	mcnpshnt // "33" Mahjong Campus Hunting 1990 Dynax
r248551	r248552
10685	10685	pitbossb // (c) 1983 Merit
10686	10686	pitbossc // (c) 1983 Merit
10687	10687	casino5 // (c) 1984 Merit
10688		mroundup // (c) 1984 Merit
	10688	mroundup // (c) 1984 Merit
10689	10689	trvwzh // (c) 1985 Merit
10690	10690	trvwzha // (c) 1985 Merit
10691	10691	trvwzhb // (c) 1985 Merit
r248551	r248552
12855	12855	quizard // (c) TAB Austria 199?
12856	12856	quizard_17 // (c) TAB Austria 1996
12857	12857	quizard_12 // (c) TAB Austria 1996
12858		quizard_10 // (c) TAB Austria 1996
	12858	quizard_10 // (c) TAB Austria 1996
12859	12859	quizard2 // (c) TAB Austria 1995
12860	12860	quizard2_22 // (c) TAB Austria 199?
12861	12861	quizard3 // (c) TAB Austria 1996

trunk/src/mame/audio/seibu.h
r248551	r248552
195	195	MCFG_CPU_PROGRAM_MAP(seibu3_adpcm_sound_map) \
196	196	MCFG_DEVICE_ADD("seibu_sound", SEIBU_SOUND, 0)
197	197
198		#define SEIBU_SOUND_SYSTEM_ENCRYPTED_LOW() \
199		MCFG_DEVICE_MODIFY("seibu_sound") \
200		downcast<seibu_sound_device *>(device)->set_encryption(1); \
201		MCFG_DEVICE_MODIFY("audiocpu") \
	198	#define SEIBU_SOUND_SYSTEM_ENCRYPTED_LOW() \
	199	MCFG_DEVICE_MODIFY("seibu_sound") \
	200	downcast<seibu_sound_device *>(device)->set_encryption(1); \
	201	MCFG_DEVICE_MODIFY("audiocpu") \
202	202	MCFG_CPU_DECRYPTED_OPCODES_MAP(seibu_sound_decrypted_opcodes_map)
203	203
204		#define SEIBU_SOUND_SYSTEM_ENCRYPTED_FULL() \
205		MCFG_DEVICE_MODIFY("seibu_sound") \
206		downcast<seibu_sound_device *>(device)->set_encryption(2); \
207		MCFG_DEVICE_MODIFY("audiocpu") \
	204	#define SEIBU_SOUND_SYSTEM_ENCRYPTED_FULL() \
	205	MCFG_DEVICE_MODIFY("seibu_sound") \
	206	downcast<seibu_sound_device *>(device)->set_encryption(2); \
	207	MCFG_DEVICE_MODIFY("audiocpu") \
208	208	MCFG_CPU_DECRYPTED_OPCODES_MAP(seibu_sound_decrypted_opcodes_map)
209	209
210		#define SEIBU_SOUND_SYSTEM_ENCRYPTED_CUSTOM() \
211		MCFG_DEVICE_MODIFY("seibu_sound") \
212		downcast<seibu_sound_device *>(device)->set_encryption(3); \
213		MCFG_DEVICE_MODIFY("audiocpu") \
	210	#define SEIBU_SOUND_SYSTEM_ENCRYPTED_CUSTOM() \
	211	MCFG_DEVICE_MODIFY("seibu_sound") \
	212	downcast<seibu_sound_device *>(device)->set_encryption(3); \
	213	MCFG_DEVICE_MODIFY("audiocpu") \
214	214	MCFG_CPU_DECRYPTED_OPCODES_MAP(seibu_sound_decrypted_opcodes_map)
215	215
216	216	#define SEIBU_SOUND_SYSTEM_YM3812_INTERFACE(freq1,freq2) \

trunk/src/mame/drivers/aerofgt.c
r248551	r248552
1521	1521	MCFG_CPU_ADD("audiocpu",Z80,8000000/2) /* 4 MHz ??? */
1522	1522	MCFG_CPU_PROGRAM_MAP(karatblzbl_sound_map)
1523	1523
1524		// MCFG_MACHINE_START_OVERRIDE(aerofgt_state,aerofgt)
1525		// MCFG_MACHINE_RESET_OVERRIDE(aerofgt_state,aerofgt)
	1524	// MCFG_MACHINE_START_OVERRIDE(aerofgt_state,aerofgt)
	1525	// MCFG_MACHINE_RESET_OVERRIDE(aerofgt_state,aerofgt)
1526	1526
1527	1527	/* video hardware */
1528	1528	MCFG_SCREEN_ADD("screen", RASTER)
r248551	r248552
1554	1554	/* sound hardware */
1555	1555	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1556	1556
1557		// NEC D7759c + YM????
	1557	// NEC D7759c + YM????
1558	1558	MACHINE_CONFIG_END
1559	1559
1560	1560	static MACHINE_CONFIG_START( spinlbrk, aerofgt_state )
r248551	r248552
2480	2480	ROM_LOAD16_BYTE( "gfx21.u71", 0x2c0000, 0x020000, CRC(ffd66ea0) SHA1(fc1b2fa27d28a61b381e3d4f15809c740082d07f) )
2481	2481	ROM_LOAD16_BYTE( "gfx26.u76", 0x2c0001, 0x020000, CRC(7ae76103) SHA1(5c42fbe133cbf600d2150295a70a1541b79706b5) )
2482	2482	ROM_LOAD16_BYTE( "gfx25.u67", 0x300000, 0x020000, CRC(1195b559) SHA1(2fd00b3360df5f0a762569ab49c445b68568cf2e) )
2483		ROM_LOAD16_BYTE( "gfx30.u72", 0x300001, 0x020000, CRC(7593679f) SHA1(3a6199d1dc60d2c05084fe41c639228613831d99) )
	2483	ROM_LOAD16_BYTE( "gfx30.u72", 0x300001, 0x020000, CRC(7593679f) SHA1(3a6199d1dc60d2c05084fe41c639228613831d99) )
2484	2484
2485	2485	ROM_REGION( 0x100000, "gfx4", 0 )
2486	2486	ROM_LOAD16_BYTE( "5.u62", 0x000000, 0x040000, CRC(1ed12174) SHA1(1e4fc511ad644aaf90505f7930957b4adf9f6c2a) )

trunk/src/mame/drivers/aleisttl.c
r248551	r248552
7	7	Chase (aka Chase1) (1976)
8	8	Deluxe Soccer (1973)
9	9	Fire Power (1975) EG-1020-2
10		Fütsball (1975)
	10	F??tsball (1975)
11	11	Galaxy Raider (1974)
12	12	Hesitation (1974) AL-6500?
13	13	Hockey, Soccer, Tennis (1974)

trunk/src/mame/drivers/appoooh.c
r248551	r248552
393	393	void appoooh_state::machine_start()
394	394	{
395	395	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0xa000, 0x6000);
396
	396
397	397	save_item(NAME(m_adpcm_data));
398	398	save_item(NAME(m_adpcm_address));
399	399	}

trunk/src/mame/drivers/arkanoid.c
r248551	r248552
1366	1366
1367	1367	/* ROMs */
1368	1368	/* rom numbering, with guesses:
1369		A75 01 = Z80 code 1/2 v1.0 Japan
1370		A75 01-1 = Z80 code 1/2 v1.1 Japan and USA/Romstar
1371		A75 02 = Z80 code 2/2 v1.0 Japan
1372		A75 03 = GFX 1/3
1373		A75 04 = GFX 2/3
1374		A75 05 = GFX 3/3
1375		A75 06 = MC68705P5 MCU code, v1.0 Japan and v1.0 USA/Romstar
1376		A75 07 = PROM red
1377		A75 08 = PROM green
1378		A75 09 = PROM blue
1379		A75 10 = Z80 code 2/2 v1.1 USA/Romstar
1380		A75 11 = Z80 code 2/2 v1.2 Japan (paired with 01-1 v1.1 Japan)
1381		(A75 12 through 17 are unknown, could be another two sets of z80 code plus mc68705p5)
1382		A75 18 = Z80 code v2.0 2/2 USA/Romstar
1383		A75 19 = Z80 code v2.0 1/2 USA/Romstar
1384		A75 20 = MC68705P5 MCU code, v2.0 USA/Romstar
1385		A75 21 = Z80 code v2.0 1/2 Japan
1386		A75 22 = Z80 code v2.0 2/2 Japan
1387		A75 23 = MC68705P5 MCU code, v2.0 Japan
1388		A75 24 = Z80 code v2.1 1/2 Japan
1389		A75 25 = Z80 code v2.1 2/2 Japan
1390		A75 26 = MC68705P5 MCU code, v2.1 Japan
1391		A75 27 = Z80 code 1/2 Tournament
1392		A75 28 = Z80 code 2/2 Tournament
1393		A75 29 = GFX 1/3 Tournament
1394		A75 30 = GFX 2/3 Tournament
1395		A75 31 = GFX 3/3 Tournament
1396		A75 32 = MC68705P5 MCU code, Tournament
1397		A75 33 = PROM red Tournament
1398		A75 34 = PROM green Tournament
1399		A75 35 = PROM blue Tournament
1400		(one of the 21/22/23 or 24/25/26 sets is likely 'world'? or are these really two japan sets?)
	1369	A75 01 = Z80 code 1/2 v1.0 Japan
	1370	A75 01-1 = Z80 code 1/2 v1.1 Japan and USA/Romstar
	1371	A75 02 = Z80 code 2/2 v1.0 Japan
	1372	A75 03 = GFX 1/3
	1373	A75 04 = GFX 2/3
	1374	A75 05 = GFX 3/3
	1375	A75 06 = MC68705P5 MCU code, v1.0 Japan and v1.0 USA/Romstar
	1376	A75 07 = PROM red
	1377	A75 08 = PROM green
	1378	A75 09 = PROM blue
	1379	A75 10 = Z80 code 2/2 v1.1 USA/Romstar
	1380	A75 11 = Z80 code 2/2 v1.2 Japan (paired with 01-1 v1.1 Japan)
	1381	(A75 12 through 17 are unknown, could be another two sets of z80 code plus mc68705p5)
	1382	A75 18 = Z80 code v2.0 2/2 USA/Romstar
	1383	A75 19 = Z80 code v2.0 1/2 USA/Romstar
	1384	A75 20 = MC68705P5 MCU code, v2.0 USA/Romstar
	1385	A75 21 = Z80 code v2.0 1/2 Japan
	1386	A75 22 = Z80 code v2.0 2/2 Japan
	1387	A75 23 = MC68705P5 MCU code, v2.0 Japan
	1388	A75 24 = Z80 code v2.1 1/2 Japan
	1389	A75 25 = Z80 code v2.1 2/2 Japan
	1390	A75 26 = MC68705P5 MCU code, v2.1 Japan
	1391	A75 27 = Z80 code 1/2 Tournament
	1392	A75 28 = Z80 code 2/2 Tournament
	1393	A75 29 = GFX 1/3 Tournament
	1394	A75 30 = GFX 2/3 Tournament
	1395	A75 31 = GFX 3/3 Tournament
	1396	A75 32 = MC68705P5 MCU code, Tournament
	1397	A75 33 = PROM red Tournament
	1398	A75 34 = PROM green Tournament
	1399	A75 35 = PROM blue Tournament
	1400	(one of the 21/22/23 or 24/25/26 sets is likely 'world'? or are these really two japan sets?)
1401	1401	*/
1402	1402
1403	1403	ROM_START( arkanoid )

trunk/src/mame/drivers/atarisy1.c
r248551	r248552
2316	2316	// set in the first place)
2317	2317	ROM_LOAD( "135048-1172.d1", 0x000000, 0x000200, CRC(b79d1903) SHA1(8319fab8b39f708457eb1efe47789b26adc61249) )
2318	2318	ROM_LOAD( "135048-1171.d2", 0x000200, 0x000200, CRC(29248a95) SHA1(c9467d495676d323121c92c6757e73b2ed3fb3d7) )
2319
	2319
2320	2320	ROM_LOAD( "136048-1174.12d", 0x000000, 0x000200, CRC(db4a4d53) SHA1(c5468f3585ec9bc23c9ee990b3ae3738b0309823) )
2321	2321	ROM_LOAD( "136048-1173.2d", 0x000200, 0x000200, CRC(c80574af) SHA1(9a3dc83f70e79915ce0db3e6e69b5dcfee3acb6f) )
2322	2322

trunk/src/mame/drivers/atarisy2.c
r248551	r248552
277	277	{
278	278	/*static const int bankoffset[64] =
279	279	{
280		12, 8, 4, 0,
281		13, 9, 5, 1,
282		14, 10, 6, 2,
283		15, 11, 7, 3,
284		28, 24, 20, 16,
285		29, 25, 21, 17,
286		30, 26, 22, 18,
287		31, 27, 23, 19,
288		44, 40, 36, 32,
289		45, 41, 37, 33,
290		46, 42, 38, 34,
291		47, 43, 39, 35,
292		60, 56, 52, 48,
293		61, 57, 53, 49,
294		62, 58, 54, 50,
295		63, 59, 55, 51
	280	12, 8, 4, 0,
	281	13, 9, 5, 1,
	282	14, 10, 6, 2,
	283	15, 11, 7, 3,
	284	28, 24, 20, 16,
	285	29, 25, 21, 17,
	286	30, 26, 22, 18,
	287	31, 27, 23, 19,
	288	44, 40, 36, 32,
	289	45, 41, 37, 33,
	290	46, 42, 38, 34,
	291	47, 43, 39, 35,
	292	60, 56, 52, 48,
	293	61, 57, 53, 49,
	294	62, 58, 54, 50,
	295	63, 59, 55, 51
296	296	};*/
297	297
298	298	int banknumber = ((data >> 10) & 0x3f) ^ 0x03;
299	299	banknumber = BITSWAP16(banknumber, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 1, 0, 3, 2);
300
	300
301	301	if (offset)
302	302	m_rombank2->set_entry(banknumber);
303	303	else

trunk/src/mame/drivers/bmcpokr.c
r248551	r248552
622	622	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 ) // NOTE
623	623	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) // KEY DOWN
624	624	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Pay Out") PORT_CODE(KEYCODE_O) // PAY
625		PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HOPPER
	625	PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HOPPER
626	626	PORT_SERVICE_NO_TOGGLE( 0x0400, IP_ACTIVE_LOW ) // ACCOUNT
627	627	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Reset") // RESET
628	628	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // (unused)

trunk/src/mame/drivers/chihiro.c
r248551	r248552
1543	1543	usb_ohci_read_endpoint_descriptor(ohcist.hc_regs[HcControlCurrentED]);
1544	1544	// only if it is not halted and not to be skipped
1545	1545	if (!(ohcist.endpoint_descriptor.h \| ohcist.endpoint_descriptor.k)) {
1546		// compare the Endpoint Descriptors TailPointer and NextTransferDescriptor fields.
	1546	// compare the Endpoint Descriptor?s TailPointer and NextTransferDescriptor fields.
1547	1547	if (ohcist.endpoint_descriptor.headp != ohcist.endpoint_descriptor.tailp) {
1548	1548	UINT32 a, b;
1549	1549	// service transfer descriptor

trunk/src/mame/drivers/coolridr.c
r248551	r248552
345	345	// store the blit params here
346	346	UINT32 m_spriteblit[12];
347	347	UINT32 m_vregs_address;
348
	348
349	349	UINT32 m_clipvals[2][3];
350	350	UINT8 m_clipblitterMode[2]; // hack
351	351
r248551	r248552
2732	2732
2733	2733	do{
2734	2734	cmd = (m_framebuffer_vram[(0+dma_index)/4] & 0xfc000000) >> 24;
2735
	2735
2736	2736	switch(cmd)
2737	2737	{
2738	2738	case 0x00: /* end of list marker */
r248551	r248552
3026	3026	AM_RANGE(0x05000000, 0x05000fff) AM_RAM
3027	3027	AM_RANGE(0x05200000, 0x052001ff) AM_RAM
3028	3028	AM_RANGE(0x05300000, 0x0530ffff) AM_RAM AM_SHARE("share3") /Communication area RAM/
3029		// AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7032_r,sh7032_w,0xffffffff) // SH-7032H internal i/o
	3029	// AM_RANGE(0x05fffe00, 0x05ffffff) AM_READWRITE16(sh7032_r,sh7032_w,0xffffffff) // SH-7032H internal i/o
3030	3030	AM_RANGE(0x06000000, 0x060001ff) AM_RAM AM_SHARE("nvram") // backup RAM
3031	3031	AM_RANGE(0x06100000, 0x06100003) AM_READ_PORT("IN0") AM_WRITE8(lamps_w,0x000000ff)
3032	3032	AM_RANGE(0x06100004, 0x06100007) AM_READ_PORT("IN1")
r248551	r248552
3123	3123	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) ) \
3124	3124	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) ) \
3125	3125	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) \
3126		PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED ) \
3127
	3126	PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED )
3128	3127	static INPUT_PORTS_START( aquastge )
3129	3128	DUMMY_INPUT_PORT("IN0")
3130	3129
3131	3130	PORT_START("IN1")
3132		PORT_DIPNAME( 0x00000001, 0x00000001, "IN1" )
3133		PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
3134		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3135		PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
3136		PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
3137		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3138		PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
3139		PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
3140		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3141		PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
3142		PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
3143		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3144		PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
3145		PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
3146		PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
3147		PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
3148		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3149		PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
3150		PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
3151		PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3131	PORT_DIPNAME( 0x00000001, 0x00000001, "IN1" )
	3132	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	3133	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3134	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	3135	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	3136	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3137	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	3138	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	3139	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3140	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	3141	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	3142	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3143	PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
	3144	PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
	3145	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	3146	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	3147	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	3148	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	3149	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	3150	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
3152	3151	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("P1 Coin")
3153	3152	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("P2 Coin")
3154	3153	PORT_SERVICE_NO_TOGGLE( 0x00040000, IP_ACTIVE_LOW )
r248551	r248552
3157	3156	PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("P2 Start")
3158	3157	PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("P2 Service Switch")
3159	3158	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNUSED )
3160		PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED )
3161
	3159	PORT_BIT( 0xff00ff00, IP_ACTIVE_LOW, IPT_UNUSED )
	3160
3162	3161	DUMMY_INPUT_PORT("IN2")
3163	3162
3164	3163	DUMMY_INPUT_PORT("IN3")
r248551	r248552
3906	3905	return 0;
3907	3906	else
3908	3907	{
3909		// printf("pc %08x\n", pc);
	3908	// printf("pc %08x\n", pc);
3910	3909	}
3911	3910
3912	3911	return m_sysh1_workram_h[0xc3fd8/4];
r248551	r248552
3933	3932	{
3934	3933	m_maincpu->space(AS_PROGRAM).install_read_handler(0x60c3fd8, 0x60c3fdb, read32_delegate(FUNC(coolridr_state::aquastge_hack_r), this));
3935	3934
3936
3937	3935
3938	3936
	3937
3939	3938	m_maincpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
3940	3939	m_subcpu->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
3941	3940
r248551	r248552
3944	3943
3945	3944	GAME( 1995, coolridr, 0, coolridr, coolridr, coolridr_state, coolridr, ROT0, "Sega", "Cool Riders",GAME_IMPERFECT_SOUND) // region is set in test mode, this set is for Japan, USA and Export (all regions)
3946	3945	GAME( 1995, aquastge, 0, aquastge, aquastge, coolridr_state, aquastge, ROT0, "Sega", "Aqua Stage",GAME_NOT_WORKING)
3947

trunk/src/mame/drivers/cps2.c
r248551	r248552
1494	1494	ROM_LOAD16_WORD_SWAP( "19x.11m", 0x000000, 0x200000, CRC(d38beef3) SHA1(134e961b926a97cca5e45d3558efb98f6f278e08) )
1495	1495	ROM_LOAD16_WORD_SWAP( "19x.12m", 0x200000, 0x200000, CRC(d47c96e2) SHA1(3c1b5563f8e7ee1c450b3592fcb319e928caec3c) )
1496	1496
1497		_19XX_ASIA_KEY
	1497	_19XX_ASIA_KEY
1498	1498	ROM_END
1499	1499
1500	1500	ROM_START( 19xxar1 )
r248551	r248552
2677	2677	ROM_REGION( 0x400000, "qsound", 0 ) /* QSound samples */
2678	2678	ROM_LOAD16_WORD_SWAP( "dad.11m", 0x000000, 0x200000, CRC(0c499b67) SHA1(a8ebd8a1cd6dece8344b7cb0439d85843fb97616) )
2679	2679	ROM_LOAD16_WORD_SWAP( "dad.12m", 0x200000, 0x200000, CRC(2f0b5a4e) SHA1(8d1ebbb811aa469b0f0d29d719d2b9af28fb63a2) )
2680
	2680
2681	2681	DDTOD_HISPANIC_KEY
2682	2682	ROM_END
2683	2683
r248551	r248552
6288	6288	ROM_REGION( 0x400000, "qsound", 0 ) /* QSound samples */
6289	6289	ROM_LOAD16_WORD_SWAP( "sz2.11m", 0x000000, 0x200000, CRC(aa47a601) SHA1(a4d1ee89c84a3b9db06469bb66e85293b5aa9ac9) )
6290	6290	ROM_LOAD16_WORD_SWAP( "sz2.12m", 0x200000, 0x200000, CRC(2237bc53) SHA1(96d5693047e4cf1ed10a8ee1905cea267a278e92) )
6291
	6291
6292	6292	SFA2_WORLD_KEY
6293	6293	ROM_END
6294	6294
r248551	r248552
8488	8488	ROM_REGION( 0x400000, "qsound", 0 ) /* QSound samples */
8489	8489	ROM_LOAD16_WORD_SWAP( "xmn.11m", 0x000000, 0x200000, CRC(c848a6bc) SHA1(ac8ac564d3c43225822f8bc330eba9f35b24b0a4) )
8490	8490	ROM_LOAD16_WORD_SWAP( "xmn.12m", 0x200000, 0x200000, CRC(729c188f) SHA1(3279774ad8aebbcf0fc779cdfcbe21044dd192ad) )
8491
	8491
8492	8492	XMCOTA_JAPAN_KEY
8493	8493	ROM_END
8494	8494

trunk/src/mame/drivers/ddenlovr.c
r248551	r248552
3921	3921	{
3922	3922	m_prot_val = data;
3923	3923
3924		set_led_status(machine(), 0, data & 0x01); // led? 1 in-game, 0 in service mode / while booting
	3924	set_led_status(machine(), 0, data & 0x01); // led? 1 in-game, 0 in service mode / while booting
3925	3925
3926		coin_counter_w(machine(), 0, data & 0x04); // coin-out
3927		coin_counter_w(machine(), 1, data & 0x08); // coin-in
	3926	coin_counter_w(machine(), 0, data & 0x04); // coin-out
	3927	coin_counter_w(machine(), 1, data & 0x08); // coin-in
3928	3928
3929	3929	if (data & 0xf2)
3930	3930	logerror("%04x: warning, coin counter = %02x\n", space.device().safe_pc(), data);

trunk/src/mame/drivers/deadang.c
r248551	r248552
166	166	PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Controller ) ) PORT_DIPLOCATION("SW2:4")
167	167	PORT_DIPSETTING( 0x0800, DEF_STR( Trackball ) )
168	168	PORT_DIPSETTING( 0x0000, DEF_STR( Joystick ) )
169
	169
170	170	PORT_START("TRACKX")
171	171	PORT_BIT( 0x0fff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(30) PORT_PLAYER(1)
172	172

trunk/src/mame/drivers/deco32.c
r248551	r248552
3643	3643	{
3644	3644	deco56_decrypt_gfx(machine(), "gfx1");
3645	3645	deco56_decrypt_gfx(machine(), "gfx2");
3646
	3646
3647	3647	save_item(NAME(m_raster_enable));
3648	3648	save_item(NAME(m_nslasher_sound_irq));
3649	3649	save_item(NAME(m_irq_source));
r248551	r248552
3725	3725
3726	3726	memcpy(RAM+0x300000,RAM+0x100000,0x100000);
3727	3727	memset(RAM+0x100000,0,0x100000);
3728
	3728
3729	3729	save_item(NAME(m_raster_enable));
3730	3730	save_item(NAME(m_nslasher_sound_irq));
3731	3731	save_item(NAME(m_irq_source));
r248551	r248552
3752	3752
3753	3753	deco56_decrypt_gfx(machine(), "gfx1"); /* 141 */
3754	3754	deco56_decrypt_gfx(machine(), "gfx2"); /* 141 */
3755
	3755
3756	3756	save_item(NAME(m_tattass_eprom_bit));
3757	3757	save_item(NAME(m_lastClock));
3758	3758	save_item(NAME(m_buffer));
r248551	r248552
3783	3783	deco156_decrypt(machine());
3784	3784
3785	3785	soundlatch_setclearedvalue(0xff);
3786
	3786
3787	3787	save_item(NAME(m_nslasher_sound_irq));
3788	3788
3789	3789	/* The board for Night Slashers is very close to the Fighter's History and

trunk/src/mame/drivers/destroyr.c
r248551	r248552
476	476	{
477	477	m_dial_timer = timer_alloc(TIMER_DESTROYR_DIAL);
478	478	m_frame_timer = timer_alloc(TIMER_DESTROYR_FRAME);
479
	479
480	480	save_item(NAME(m_cursor));
481	481	save_item(NAME(m_wavemod));
482	482	save_item(NAME(m_attract));

trunk/src/mame/drivers/dreamwld.c
r248551	r248552
353	353	int x0 = 0, x1 = 0;
354	354
355	355	UINT16* linebase;
356
357
358	356
	357
	358
359	359	/* layer 0 */
360	360	linebase = &m_lineram16[0x000];
361	361
r248551	r248552
367	367	else
368	368	/* per-line rowscroll */
369	369	x0 = linebase[(i+32)&0xff];
370		}
	370	}
371	371
372	372	tmptilemap0->set_scrollx(
373	373	(i + layer0_scrolly) & 0x3ff,
r248551	r248552
408	408
409	409	READ32_MEMBER(dreamwld_state::dreamwld_protdata_r)
410	410	{
411		//static int count = 0;
	411	//static int count = 0;
412	412
413	413	UINT8 *protdata = memregion("user1")->base();
414	414	size_t protsize = memregion("user1")->bytes();
415	415	UINT8 dat = protdata[(m_protindex++) % protsize];
416	416
417		//printf("protection read %04x %02x\n", count, dat);
418		//count++;
	417	//printf("protection read %04x %02x\n", count, dat);
	418	//count++;
419	419
420	420	// real hw returns 00 after end of data, I haven't checked if it's possible to overflow the read counter
421	421	// and read out the internal rom.
r248551	r248552
1249	1249
1250	1250	GAME( 1997, baryon, 0, baryon, baryon, driver_device, 0, ROT270, "SemiCom / Tirano", "Baryon - Future Assault (set 1)", GAME_SUPPORTS_SAVE )
1251	1251	GAME( 1997, baryona, baryon, baryon, baryon, driver_device, 0, ROT270, "SemiCom / Tirano", "Baryon - Future Assault (set 2)", GAME_SUPPORTS_SAVE )
1252		GAME( 1998, cutefght, 0, dreamwld, cutefght, driver_device, 0, ROT0, "SemiCom", "Cute Fighter", GAME_SUPPORTS_SAVE )
	1252	GAME( 1998, cutefght, 0, dreamwld, cutefght, driver_device, 0, ROT0, "SemiCom", "Cute Fighter", GAME_SUPPORTS_SAVE )
1253	1253	GAME( 1999, rolcrush, 0, baryon, rolcrush, driver_device, 0, ROT0, "Trust / SemiCom", "Rolling Crush (version 1.07.E - 1999/02/11)", GAME_SUPPORTS_SAVE )
1254	1254	GAME( 1999, gaialast, 0, baryon, gaialast, driver_device, 0, ROT0, "SemiCom / XESS", "Gaia - The Last Choice of Earth", GAME_SUPPORTS_SAVE )
1255	1255	GAME( 2000, dreamwld, 0, dreamwld, dreamwld, driver_device, 0, ROT0, "SemiCom", "Dream World", GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/dynax.c
r248551	r248552
4811	4811	MACHINE_CONFIG_END
4812	4812
4813	4813	static MACHINE_CONFIG_DERIVED( mjembase, hnoridur )
4814		MCFG_CPU_MODIFY("maincpu") // TMPZ84015
	4814	MCFG_CPU_MODIFY("maincpu") // TMPZ84015
4815	4815	MCFG_CPU_PROGRAM_MAP(nanajign_mem_map)
4816	4816	MCFG_CPU_IO_MAP(mjembase_io_map)
4817	4817	MCFG_CPU_VBLANK_INT_DRIVER("screen", dynax_state, mjelctrn_vblank_interrupt) /* IM 2 needs a vector on the data bus */
r248551	r248552
5456	5456
5457	5457	}
5458	5458	}
5459
5460	5459
	5460
5461	5461	DRIVER_INIT_MEMBER(dynax_state, maya_common)
5462	5462	{
5463	5463	/* Address lines scrambling on 1 z80 rom */

trunk/src/mame/drivers/firebeat.c
r248551	r248552
227	227
228	228	switch (reg)
229	229	{
230		case 0x78: // GCU Status
	230	case 0x78: // GCU Status
231	231	/* ppd checks bits 0x0041 of the upper halfword on interrupt */
232	232	return 0xffff0005;
233	233
r248551	r248552
255	255	#endif
256	256	break;
257	257
258		case 0x14: // ?
	258	case 0x14: // ?
259	259	break;
260	260
261		case 0x18: // ?
	261	case 0x18: // ?
262	262	break;
263	263
264		case 0x20: // Framebuffer 0 Origin(?)
	264	case 0x20: // Framebuffer 0 Origin(?)
265	265	break;
266	266
267		case 0x24: // Framebuffer 1 Origin(?)
	267	case 0x24: // Framebuffer 1 Origin(?)
268	268	break;
269	269
270		case 0x28: // Framebuffer 2 Origin(?)
	270	case 0x28: // Framebuffer 2 Origin(?)
271	271	break;
272	272
273		case 0x2c: // Framebuffer 3 Origin(?)
	273	case 0x2c: // Framebuffer 3 Origin(?)
274	274	break;
275	275
276		case 0x30: // Framebuffer 0 Dimensions
	276	case 0x30: // Framebuffer 0 Dimensions
277	277	if (ACCESSING_BITS_16_31)
278	278	m_frame[0].height = (data >> 16) & 0xffff;
279	279	if (ACCESSING_BITS_0_15)
280	280	m_frame[0].width = data & 0xffff;
281	281	break;
282	282
283		case 0x34: // Framebuffer 1 Dimensions
	283	case 0x34: // Framebuffer 1 Dimensions
284	284	if (ACCESSING_BITS_16_31)
285	285	m_frame[1].height = (data >> 16) & 0xffff;
286	286	if (ACCESSING_BITS_0_15)
287	287	m_frame[1].width = data & 0xffff;
288	288	break;
289	289
290		case 0x38: // Framebuffer 2 Dimensions
	290	case 0x38: // Framebuffer 2 Dimensions
291	291	if (ACCESSING_BITS_16_31)
292	292	m_frame[2].height = (data >> 16) & 0xffff;
293	293	if (ACCESSING_BITS_0_15)
294	294	m_frame[2].width = data & 0xffff;
295	295	break;
296	296
297		case 0x3c: // Framebuffer 3 Dimensions
	297	case 0x3c: // Framebuffer 3 Dimensions
298	298	if (ACCESSING_BITS_16_31)
299	299	m_frame[3].height = (data >> 16) & 0xffff;
300	300	if (ACCESSING_BITS_0_15)
301	301	m_frame[3].width = data & 0xffff;
302	302	break;
303	303
304		case 0x40: // Framebuffer 0 Base
	304	case 0x40: // Framebuffer 0 Base
305	305	m_frame[0].base = data;
306	306	#if PRINT_GCU
307	307	printf("%s FB0 Base: %08X\n", basetag(), data);
308	308	#endif
309	309	break;
310	310
311		case 0x44: // Framebuffer 1 Base
	311	case 0x44: // Framebuffer 1 Base
312	312	m_frame[1].base = data;
313	313	#if PRINT_GCU
314	314	printf("%s FB1 Base: %08X\n", basetag(), data);
315	315	#endif
316	316	break;
317	317
318		case 0x48: // Framebuffer 2 Base
	318	case 0x48: // Framebuffer 2 Base
319	319	m_frame[2].base = data;
320	320	#if PRINT_GCU
321	321	printf("%s FB2 Base: %08X\n", basetag(), data);
322	322	#endif
323	323	break;
324	324
325		case 0x4c: // Framebuffer 3 Base
	325	case 0x4c: // Framebuffer 3 Base
326	326	m_frame[3].base = data;
327	327	#if PRINT_GCU
328	328	printf("%s FB3 Base: %08X\n", basetag(), data);
329	329	#endif
330	330	break;
331	331
332		case 0x5c: // VRAM Read Address
	332	case 0x5c: // VRAM Read Address
333	333	m_vram_read_addr = (data & 0xffffff) / 2;
334	334	break;
335	335
336		case 0x60: // VRAM Port 0 Write Address
	336	case 0x60: // VRAM Port 0 Write Address
337	337	m_vram_fifo0_addr = (data & 0xffffff) / 2;
338	338	break;
339	339
340		case 0x68: // VRAM Port 0/1 Mode
	340	case 0x68: // VRAM Port 0/1 Mode
341	341	if (ACCESSING_BITS_16_31)
342	342	m_vram_fifo0_mode = data >> 16;
343	343	if (ACCESSING_BITS_0_15)
344	344	m_vram_fifo1_mode = data & 0xffff;
345	345	break;
346	346
347		case 0x70: // VRAM Port 0 Write FIFO
	347	case 0x70: // VRAM Port 0 Write FIFO
348	348	if (m_vram_fifo0_mode & 0x100)
349	349	{
350	350	// write to command fifo
r248551	r248552
359	359	m_command_fifo0_ptr = 0;
360	360	}
361	361	}
362		else
	362	else
363	363	{
364	364	// write to VRAM fifo
365	365	m_vram[m_vram_fifo0_addr] = data;
r248551	r248552
367	367	}
368	368	break;
369	369
370		case 0x64: // VRAM Port 1 Write Address
	370	case 0x64: // VRAM Port 1 Write Address
371	371	m_vram_fifo1_addr = (data & 0xffffff) / 2;
372	372	printf("GCU FIFO1 addr = %08X\n", data);
373	373	break;
374	374
375		case 0x74: // VRAM Port 1 Write FIFO
	375	case 0x74: // VRAM Port 1 Write FIFO
376	376	printf("GCU FIFO1 write = %08X\n", data);
377	377
378	378	if (m_vram_fifo1_mode & 0x100)
r248551	r248552
388	388	m_command_fifo1_ptr = 0;
389	389	}
390	390	}
391		else
	391	else
392	392	{
393	393	// write to VRAM fifo
394	394	m_vram[m_vram_fifo1_addr] = data;
r248551	r248552
409	409	int x = 0;
410	410	int y = 0;
411	411	int width = m_frame[0].width;
412		int height = m_frame[0].height;
	412	int height = m_frame[0].height;
413	413
414	414	if (width != 0 && height != 0)
415	415	{
r248551	r248552
430	430	int li = ((j+y) * fb_pitch) + x;
431	431	UINT32 fbaddr0 = m_frame[0].base + li;
432	432	UINT32 fbaddr1 = m_frame[1].base + li;
433		// UINT32 fbaddr2 = m_frame[2].base + li;
434		// UINT32 fbaddr3 = m_frame[3].base + li;
	433	// UINT32 fbaddr2 = m_frame[2].base + li;
	434	// UINT32 fbaddr3 = m_frame[3].base + li;
435	435
436	436	for (int i=0; i < width; i++)
437	437	{
438	438	UINT16 pix0 = vram16[fbaddr0 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
439	439	UINT16 pix1 = vram16[fbaddr1 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
440		// UINT16 pix2 = vram16[fbaddr2 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
441		// UINT16 pix3 = vram16[fbaddr3 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
	440	// UINT16 pix2 = vram16[fbaddr2 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
	441	// UINT16 pix3 = vram16[fbaddr3 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
442	442
443	443	if (pix0 & 0x8000)
444	444	{
r248551	r248552
451	451
452	452	fbaddr0++;
453	453	fbaddr1++;
454		// fbaddr2++;
455		// fbaddr3++;
	454	// fbaddr2++;
	455	// fbaddr3++;
456	456	}
457	457	}
458	458
r248551	r248552
493	493	UINT32 address = cmd[0] & 0xffffff;
494	494	int alpha_level = (cmd[2] >> 27) & 0x1f;
495	495	bool relative_coords = (cmd[0] & 0x10000000) ? true : false;
496
	496
497	497	if (relative_coords)
498	498	{
499	499	x += m_fb_origin_x;
r248551	r248552
522	522	int index;
523	523	int xinc;
524	524	UINT32 fbaddr = ((j+y) * fb_pitch) + x;
525
	525
526	526	if (yflip)
527	527	{
528	528	index = address + ((height - 1 - (v >> 6)) * 1024);
r248551	r248552
592	592
593	593	void firebeat_gcu_device::fill_rect(UINT32 *cmd)
594	594	{
595		// 0x00: xxx----- -------- -------- -------- command (4)
	595	// 0x00: xxx----- -------- -------- -------- command (4)
596	596	// 0x00: ---x---- -------- -------- -------- 0: absolute coordinates
597	597	// 1: relative coordinates from framebuffer origin
598	598	// 0x00: ----xx-- -------- -------- -------- ?
r248551	r248552
742	742
743	743	switch (command)
744	744	{
745		case 0: // NOP?
	745	case 0: // NOP?
746	746	break;
747	747
748		case 1: // Execute display list
	748	case 1: // Execute display list
749	749	execute_display_list(cmd[0] & 0xffffff);
750	750	break;
751	751
752		case 2: // End of display list
	752	case 2: // End of display list
753	753	end = true;
754	754	break;
755	755
756		case 3: // Framebuffer config
	756	case 3: // Framebuffer config
757	757	fb_config(cmd);
758	758	break;
759	759
760		case 4: // Fill rectangle
	760	case 4: // Fill rectangle
761	761	fill_rect(cmd);
762	762	break;
763	763
764		case 5: // Draw object
	764	case 5: // Draw object
765	765	draw_object(cmd);
766	766	break;
767	767
768		case 7: // Draw 8x8 character (2 bits per pixel)
	768	case 7: // Draw 8x8 character (2 bits per pixel)
769	769	draw_character(cmd);
770	770	break;
771	771
r248551	r248552
787	787
788	788	switch (command)
789	789	{
790		case 0: // NOP?
	790	case 0: // NOP?
791	791	break;
792	792
793		case 1: // Execute display list
	793	case 1: // Execute display list
794	794	execute_display_list(cmd[0] & 0xffffff);
795	795	break;
796	796
797		case 2: // End of display list
	797	case 2: // End of display list
798	798	break;
799	799
800		case 3: // Framebuffer config
	800	case 3: // Framebuffer config
801	801	fb_config(cmd);
802	802	break;
803	803
804		case 4: // Fill rectangle
	804	case 4: // Fill rectangle
805	805	fill_rect(cmd);
806	806	break;
807	807
808		case 5: // Draw object
	808	case 5: // Draw object
809	809	draw_object(cmd);
810	810	break;
811	811
812		case 7: // Draw 8x8 character (2 bits per pixel)
	812	case 7: // Draw 8x8 character (2 bits per pixel)
813	813	draw_character(cmd);
814	814	break;
815	815
r248551	r248552
851	851	printf("dumping %s\n", filename);
852	852	FILE *file = fopen(filename, "wb");
853	853	int i;
854
	854
855	855	for (i=0; i < 0x2000000/4; i++)
856	856	{
857	857	fputc((m_vram[i] >> 24) & 0xff, file);
r248551	r248552
859	859	fputc((m_vram[i] >> 8) & 0xff, file);
860	860	fputc((m_vram[i] >> 0) & 0xff, file);
861	861	}
862
	862
863	863	fclose(file);
864	864	#endif
865	865	}
r248551	r248552
1594	1594	{
1595	1595	r \|= m_spu_shared_ram[(offset * 4) + 3] << 0;
1596	1596
1597		if (offset == 0xff) // address 0x3ff clears PPC interrupt
	1597	if (offset == 0xff) // address 0x3ff clears PPC interrupt
1598	1598	{
1599	1599	m_maincpu->set_input_line(INPUT_LINE_IRQ3, CLEAR_LINE);
1600	1600	}
r248551	r248552
1621	1621	{
1622	1622	m_spu_shared_ram[(offset * 4) + 2] = (data >> 8) & 0xff;
1623	1623
1624		if (offset == 0xff) // address 0x3fe triggers M68K interrupt
	1624	if (offset == 0xff) // address 0x3fe triggers M68K interrupt
1625	1625	{
1626	1626	m_audiocpu->set_input_line(INPUT_LINE_IRQ4, ASSERT_LINE);
1627	1627	}
r248551	r248552
1637	1637	IRQ1: ?
1638	1638
1639	1639	IRQ2: Timer?
1640
1641		IRQ4: Dual-port RAM mailbox (when PPC writes to 0x3FE)
1642		Handles commands from PPC (bytes 0x00 and 0x01)
1643
1644		IRQ6: ATA
	1640
	1641	IRQ4: Dual-port RAM mailbox (when PPC writes to 0x3FE)
	1642	Handles commands from PPC (bytes 0x00 and 0x01)
	1643
	1644	IRQ6: ATA
1645	1645	*/
1646	1646
1647	1647	READ16_MEMBER(firebeat_state::m68k_spu_share_r)
r248551	r248552
1655	1655	{
1656	1656	r \|= m_spu_shared_ram[offset];
1657	1657
1658		if (offset == 0x3fe) // address 0x3fe clears M68K interrupt
	1658	if (offset == 0x3fe) // address 0x3fe clears M68K interrupt
1659	1659	{
1660	1660	m_audiocpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE);
1661	1661	}
r248551	r248552
1672	1672	{
1673	1673	m_spu_shared_ram[offset] = data & 0xff;
1674	1674
1675		if (offset == 0x3ff) // address 0x3ff triggers PPC interrupt
	1675	if (offset == 0x3ff) // address 0x3ff triggers PPC interrupt
1676	1676	{
1677	1677	m_maincpu->set_input_line(INPUT_LINE_IRQ3, ASSERT_LINE);
1678	1678	}
r248551	r248552
1684	1684	// dipswitches?
1685	1685
1686	1686	UINT16 r = 0;
1687		r \|= 0x80; // if set, uses ATA PIO mode, otherwise DMA
	1687	r \|= 0x80; // if set, uses ATA PIO mode, otherwise DMA
1688	1688
1689	1689	return r;
1690	1690	}
r248551	r248552
1760	1760	AM_RANGE(0x280000, 0x2807ff) AM_READWRITE(m68k_spu_share_r, m68k_spu_share_w)
1761	1761	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs0, write_cs0)
1762	1762	AM_RANGE(0x340000, 0x34000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs1, write_cs1)
1763		AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rf5c400", rf5c400_device, rf5c400_r, rf5c400_w)
	1763	AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rf5c400", rf5c400_device, rf5c400_r, rf5c400_w)
1764	1764	ADDRESS_MAP_END
1765	1765
1766	1766	/*****************************************************************************/
r248551	r248552
2503	2503	// Beatmania III has a different BIOS and SPU program, and they aren't dumped yet
2504	2504	ROM_START( bm37th )
2505	2505	ROM_REGION32_BE(0x80000, "user1", 0)
2506		ROM_LOAD16_WORD_SWAP("974a03.21e", 0x00000, 0x80000, BAD_DUMP CRC(ef9a932d) SHA1(6299d3b9823605e519dbf1f105b59a09197df72f)) // boots with KBM BIOS
	2506	ROM_LOAD16_WORD_SWAP("974a03.21e", 0x00000, 0x80000, BAD_DUMP CRC(ef9a932d) SHA1(6299d3b9823605e519dbf1f105b59a09197df72f)) // boots with KBM BIOS
2507	2507
2508	2508	ROM_REGION(0xc0, "user2", ROMREGION_ERASE00) // Security dongle
2509	2509	ROM_LOAD( "gcb07-jc", 0x000000, 0x0000c0, CRC(16115b6a) SHA1(dcb2a3346973941a946b2cdfd31a5a761f666ca3) )
r248551	r248552
2522	2522
2523	2523	ROM_START( bm3final )
2524	2524	ROM_REGION32_BE(0x80000, "user1", 0)
2525		ROM_LOAD16_WORD_SWAP("974a03.21e", 0x00000, 0x80000, BAD_DUMP CRC(ef9a932d) SHA1(6299d3b9823605e519dbf1f105b59a09197df72f)) // boots with KBM BIOS
	2525	ROM_LOAD16_WORD_SWAP("974a03.21e", 0x00000, 0x80000, BAD_DUMP CRC(ef9a932d) SHA1(6299d3b9823605e519dbf1f105b59a09197df72f)) // boots with KBM BIOS
2526	2526
2527	2527	ROM_REGION(0xc0, "user2", ROMREGION_ERASE00) // Security dongle
2528	2528	ROM_LOAD( "gcc01-jc", 0x000000, 0x0000c0, CRC(9c49fed8) SHA1(212b87c1d25763117611ffb2a36ed568d429d2f4) )

trunk/src/mame/drivers/galaxian.c
r248551	r248552
6523	6523
6524	6524	DRIVER_INIT_MEMBER(galaxian_state,scobrae)
6525	6525	{
6526
6527	6526	UINT8 *rom = memregion("maincpu")->base();
6528	6527	int offs;
6529	6528

trunk/src/mame/drivers/gladiatr.c
r248551	r248552
994	994
995	995	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x6000);
996	996	membank("bank2")->configure_entries(0, 2, memregion("audiocpu")->base() + 0x10000, 0xc000);
997
	997
998	998	/* make sure bank is valid in cpu-reset */
999	999	membank("bank2")->set_entry(0);
1000	1000	}

trunk/src/mame/drivers/gstriker.c
r248551	r248552
181	181	void gstriker_state::machine_start()
182	182	{
183	183	membank("soundbank")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x8000);
184
	184
185	185	save_item(NAME(m_dmmy_8f_ret));
186	186	save_item(NAME(m_pending_command));
187	187	}
r248551	r248552
1012	1012
1013	1013	m_maincpu->space(AS_PROGRAM).install_write_handler(0x20008e, 0x20008f, write16_delegate(FUNC(gstriker_state::twrldc94_prot_reg_w),this));
1014	1014	m_maincpu->space(AS_PROGRAM).install_read_handler(0x20008e, 0x20008f, read16_delegate(FUNC(gstriker_state::twrldc94_prot_reg_r),this));
1015
	1015
1016	1016	save_item(NAME(m_mcu_data));
1017	1017	save_item(NAME(m_prot_reg));
1018	1018	}

trunk/src/mame/drivers/itech8.c
r248551	r248552
597	597	/* we need to update behind the beam as well */
598	598	m_behind_beam_update_timer = timer_alloc(TIMER_BEHIND_BEAM_UPDATE);
599	599	m_behind_beam_update_timer->adjust(m_screen->time_until_pos(0), 32);
600
	600
601	601	itech8_state::machine_start();
602	602	}
603	603
r248551	r248552
605	605	{
606	606	if (membank("bank1"))
607	607	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x4000, 0xc000);
608
	608
609	609	m_irq_off_timer = timer_alloc(TIMER_IRQ_OFF);
610	610	m_delayed_sound_data_timer = timer_alloc(TIMER_DELAYED_SOUND_DATA);
611	611	m_blitter_done_timer = timer_alloc(TIMER_BLITTER_DONE);
r248551	r248552
2611	2611	m_maincpu->space(AS_PROGRAM).install_write_handler(0x0160, 0x0160, write8_delegate(FUNC(itech8_state::grmatch_palette_w),this));
2612	2612	m_maincpu->space(AS_PROGRAM).install_write_handler(0x0180, 0x0180, write8_delegate(FUNC(itech8_state::grmatch_xscroll_w),this));
2613	2613	m_maincpu->space(AS_PROGRAM).unmap_write(0x01e0, 0x01ff);
2614
	2614
2615	2615	save_item(NAME(m_grmatch_palcontrol));
2616	2616	save_item(NAME(m_grmatch_xscroll));
2617	2617	save_item(NAME(m_grmatch_palette));
r248551	r248552
2623	2623	m_maincpu->space(AS_PROGRAM).install_read_handler (0x0180, 0x0180, read8_delegate(FUNC(itech8_state::slikshot_z80_r),this));
2624	2624	m_maincpu->space(AS_PROGRAM).install_read_handler (0x01cf, 0x01cf, read8_delegate(FUNC(itech8_state::slikshot_z80_control_r),this));
2625	2625	m_maincpu->space(AS_PROGRAM).install_write_handler(0x01cf, 0x01cf, write8_delegate(FUNC(itech8_state::slikshot_z80_control_w),this));
2626
	2626
2627	2627	m_delayed_z80_control_timer = timer_alloc(TIMER_DELAYED_Z80_CONTROL);
2628
	2628
2629	2629	save_item(NAME(m_z80_ctrl));
2630	2630	save_item(NAME(m_z80_port_val));
2631	2631	save_item(NAME(m_z80_clear_to_send));

trunk/src/mame/drivers/mazerbla.c
r248551	r248552
350	350	WRITE8_MEMBER(mazerbla_state::cfb_rom_bank_sel_w)
351	351	{
352	352	m_gfx_rom_bank = data;
353
	353
354	354	membank("bank1")->set_entry(m_gfx_rom_bank);
355	355	}
356	356
r248551	r248552
1381	1381	void mazerbla_state::machine_start()
1382	1382	{
1383	1383	membank("bank1")->configure_entries(0, 256, memregion("sub2")->base() + 0x10000, 0x2000);
1384
	1384
1385	1385	save_item(NAME(m_vcu_video_reg));
1386	1386	save_item(NAME(m_vcu_gfx_addr));
1387	1387	save_item(NAME(m_vcu_gfx_param_addr));

trunk/src/mame/drivers/mcr3.c
r248551	r248552
2035	2035	GAMEL(1983, spyhuntp, spyhunt, mcrsc_csd, spyhunt, mcr3_state, spyhunt, ROT90, "Bally Midway (Playtronic license)", "Spy Hunter (Playtronic license)", GAME_SUPPORTS_SAVE, layout_spyhunt )
2036	2036	GAME( 1984, crater, 0, mcrscroll, crater, mcr3_state, crater, ORIENTATION_FLIP_X, "Bally Midway", "Crater Raider", GAME_SUPPORTS_SAVE )
2037	2037	GAMEL(1985, turbotag, 0, mcrsc_csd, turbotag, mcr3_state, turbotag, ROT90, "Bally Midway", "Turbo Tag (prototype)", GAME_SUPPORTS_SAVE, layout_turbotag )
2038
	2038
2039	2039	// very different hardware, probably bootleg despite the license text printed on the PCB, similar to '1942p' in 1942.c. Probably should be put in separate driver.
2040	2040	// PCB made by Tecfri for Recreativos Franco S.A. in Spain, has Bally Midway logo, and licensing text on the PCB. Board is dated '85' so seems to be a low-cost rebuild? it is unclear if it made it to market.
2041	2041	GAME (1983, spyhuntpr,spyhunt, spyhuntpr, spyhuntpr,mcr3_state, spyhuntpr,ROT90, "Bally Midway (Recreativos Franco S.A. license)", "Spy Hunter (Spain, Tecfri / Recreativos Franco S.A. PCB)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/midyunit.c
r248551	r248552
2670	2670	*************************************************************************/
2671	2671
2672	2672	// same as mkyawdim3, but with its own main program roms
2673		ROM_START( mkyawdim4 )
	2673	ROM_START( mkyawdim4 )
2674	2674	ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound CPU */
2675		ROM_LOAD( "14.bin", 0x00000, 0x10000, CRC(b58d229e) SHA1(3ed14ef650dfa7f9d460611b19e9233a022cbea6) )
	2675	ROM_LOAD( "14.bin", 0x00000, 0x10000, CRC(b58d229e) SHA1(3ed14ef650dfa7f9d460611b19e9233a022cbea6) )
2676	2676
2677	2677	ROM_REGION( 0x100000, "oki", 0 ) /* ADPCM */
2678		ROM_LOAD( "15.bin", 0x00000, 0x20000, CRC(921c613d) SHA1(be62b87f195b6347112ab13cc14514d4c88a8b86) )
	2678	ROM_LOAD( "15.bin", 0x00000, 0x20000, CRC(921c613d) SHA1(be62b87f195b6347112ab13cc14514d4c88a8b86) )
2679	2679	ROM_RELOAD( 0x40000, 0x20000 )
2680	2680	ROM_RELOAD( 0x80000, 0x20000 )
2681	2681	ROM_RELOAD( 0xc0000, 0x20000 )
2682		ROM_LOAD( "16.bin", 0x20000, 0x20000, CRC(6e68e0b0) SHA1(edb7aa6507452ffa5ce7097e3b1855a69542971c) )
	2682	ROM_LOAD( "16.bin", 0x20000, 0x20000, CRC(6e68e0b0) SHA1(edb7aa6507452ffa5ce7097e3b1855a69542971c) )
2683	2683	ROM_CONTINUE( 0x60000, 0x20000 )
2684	2684	ROM_CONTINUE( 0xa0000, 0x20000 )
2685	2685	ROM_CONTINUE( 0xe0000, 0x20000 )
r248551	r248552
2687	2687	ROM_REGION16_LE( 0x100000, "user1", 0 ) /* 34010 code */
2688	2688	ROM_LOAD16_BYTE( "17.bin", 0x00000, 0x80000, CRC(671b533d) SHA1(20859ceb0635126047216f85a6e35072e14766ad) )
2689	2689	ROM_LOAD16_BYTE( "18.bin", 0x00001, 0x80000, CRC(4e857747) SHA1(b94c7d5e4356ac6890e6bfaf75c76d94408e5bc5) )
2690		// ROM_LOAD16_BYTE( "17.bin", 0x00000, 0x80000, CRC(b12b3bf2) SHA1(deb7755e8407d9de25124b3fdbc4c834a25d8252) ) // other PCB: mkyawdim3 with mkyawdim main program
2691		// ROM_LOAD16_BYTE( "18.bin", 0x00001, 0x80000, CRC(7a37dc5c) SHA1(c4fc6933d8b990c5c56c65282b1f72b90b5d5435) )
	2690	// ROM_LOAD16_BYTE( "17.bin", 0x00000, 0x80000, CRC(b12b3bf2) SHA1(deb7755e8407d9de25124b3fdbc4c834a25d8252) ) // other PCB: mkyawdim3 with mkyawdim main program
	2691	// ROM_LOAD16_BYTE( "18.bin", 0x00001, 0x80000, CRC(7a37dc5c) SHA1(c4fc6933d8b990c5c56c65282b1f72b90b5d5435) )
2692	2692
2693	2693	ROM_REGION( 0x800000, "gfx1", 0 )
2694		ROM_LOAD( "22.bin", 0x000000, 0x80000, CRC(d17096c4) SHA1(01ef390a372c9d94adf138f9543ebb88b89f4c38) )
2695		ROM_LOAD( "21.bin", 0x080000, 0x80000, CRC(993bc2e4) SHA1(7791edbec2b4b8971a3e790346dd7564ecf16d5c) )
2696		ROM_LOAD( "20.bin", 0x100000, 0x80000, CRC(6fb91ede) SHA1(a3735b49f93b08c44fbc97e2b5aad394628fbe90) )
2697		ROM_LOAD( "19.bin", 0x180000, 0x80000, CRC(ed1ff88a) SHA1(6b090b658ee6148af953bd0c9216f37162b6460f) )
	2694	ROM_LOAD( "22.bin", 0x000000, 0x80000, CRC(d17096c4) SHA1(01ef390a372c9d94adf138f9543ebb88b89f4c38) )
	2695	ROM_LOAD( "21.bin", 0x080000, 0x80000, CRC(993bc2e4) SHA1(7791edbec2b4b8971a3e790346dd7564ecf16d5c) )
	2696	ROM_LOAD( "20.bin", 0x100000, 0x80000, CRC(6fb91ede) SHA1(a3735b49f93b08c44fbc97e2b5aad394628fbe90) )
	2697	ROM_LOAD( "19.bin", 0x180000, 0x80000, CRC(ed1ff88a) SHA1(6b090b658ee6148af953bd0c9216f37162b6460f) )
2698	2698
2699		ROM_LOAD( "26.bin", 0x200000, 0x80000, CRC(a002a155) SHA1(3cf7909e92bcd428063596fc5b9953e0000d6eca) )
2700		ROM_LOAD( "25.bin", 0x280000, 0x80000, CRC(dcee8492) SHA1(a912b74d3b26ebd1b1613cc631080f83ececeaf8) )
2701		ROM_LOAD( "24.bin", 0x300000, 0x80000, CRC(de88caef) SHA1(a7927b504dc56ca5c9048373977fe5743b0a3f0b) )
2702		ROM_LOAD( "23.bin", 0x380000, 0x80000, CRC(37eb01b4) SHA1(06092460bd137e08d0f8df8560942ed877d40e09) )
	2699	ROM_LOAD( "26.bin", 0x200000, 0x80000, CRC(a002a155) SHA1(3cf7909e92bcd428063596fc5b9953e0000d6eca) )
	2700	ROM_LOAD( "25.bin", 0x280000, 0x80000, CRC(dcee8492) SHA1(a912b74d3b26ebd1b1613cc631080f83ececeaf8) )
	2701	ROM_LOAD( "24.bin", 0x300000, 0x80000, CRC(de88caef) SHA1(a7927b504dc56ca5c9048373977fe5743b0a3f0b) )
	2702	ROM_LOAD( "23.bin", 0x380000, 0x80000, CRC(37eb01b4) SHA1(06092460bd137e08d0f8df8560942ed877d40e09) )
2703	2703
2704		ROM_LOAD( "30.bin", 0x400000, 0x80000, CRC(45acaf21) SHA1(5edd36c55f4e5d3c74fb85171728ec0a58284b12) )
2705		ROM_LOAD( "29.bin", 0x480000, 0x80000, CRC(2a6c10a0) SHA1(cc90923c44f2961b945a0fd0f85ecc2ba04af2cb) )
2706		ROM_LOAD( "28.bin", 0x500000, 0x80000, CRC(23308979) SHA1(0b36788624a1cf0d3f4c895be5ba967b8dfcf85e) )
2707		ROM_LOAD( "27.bin", 0x580000, 0x80000, CRC(cafc47bb) SHA1(8610af6e52f7089ff4acd850c53ab8b4119e4445) )
2708		ROM_END
	2704	ROM_LOAD( "30.bin", 0x400000, 0x80000, CRC(45acaf21) SHA1(5edd36c55f4e5d3c74fb85171728ec0a58284b12) )
	2705	ROM_LOAD( "29.bin", 0x480000, 0x80000, CRC(2a6c10a0) SHA1(cc90923c44f2961b945a0fd0f85ecc2ba04af2cb) )
	2706	ROM_LOAD( "28.bin", 0x500000, 0x80000, CRC(23308979) SHA1(0b36788624a1cf0d3f4c895be5ba967b8dfcf85e) )
	2707	ROM_LOAD( "27.bin", 0x580000, 0x80000, CRC(cafc47bb) SHA1(8610af6e52f7089ff4acd850c53ab8b4119e4445) )
	2708	ROM_END
2709	2709
2710	2710
2711	2711

trunk/src/mame/drivers/mmagic.c
r248551	r248552
2	2	// copyright-holders:Dirk Best
3	3	/***************************************************************************
4	4
5		"Monkey Magic" © 1979 Nintendo
	5	"Monkey Magic" ?? 1979 Nintendo
6	6
7	7
8		Dumping info provided by Andrew Welburn:
	8	Dumping info provided by Andrew Welburn:
9	9
10		TZF-MP - Main Board
11		TZF-SOU - Sound Board
	10	TZF-MP - Main Board
	11	TZF-SOU - Sound Board
12	12
13		# device Label PCB filename
14		-------------------------------------------
15		4 i2708 1AI* 2A 1AI.2A
16		5 i2708 2AI* 3A 2AI.3A
17		6 i2708 3AI* 4A 3AI.4A
18		7 i2708 4AI* 4/5A 4AI.45A
19		8 i2708 5AI* 5A 5AI.5A
	13	# device Label PCB filename
	14	-------------------------------------------
	15	4 i2708 1AI* 2A 1AI.2A
	16	5 i2708 2AI* 3A 2AI.3A
	17	6 i2708 3AI* 4A 3AI.4A
	18	7 i2708 4AI* 4/5A 4AI.45A
	19	8 i2708 5AI* 5A 5AI.5A
20	20
21		22 H7641 6H 6HI 6H.6HI
22		23 ?? ** 7H 7HI 7H.7HI
23		24 H7641 6J 6JK 6J.6JK
24		25 H7641 6H*** 7JK
	21	22 H7641 6H 6HI 6H.6HI
	22	23 ?? ** 7H 7HI 7H.7HI
	23	24 H7641 6J 6JK 6J.6JK
	24	25 H7641 6H*** 7JK
25	25
26		* Note that there is a Kana character 'I' in romaji on the end of the labels, not an I.
	26	* Note that there is a Kana character 'I' in romaji on the end of the labels, not an I.
27	27
28		** Note this device was plastic and not ceramic, but it was dumped as a Harris 7641 as
29		it is logical that its compatible with the 7641. I can see the other devices all have
30		similar/same Harris markings in the bottom left of the IC obscured by the labels.
	28	** Note this device was plastic and not ceramic, but it was dumped as a Harris 7641 as
	29	it is logical that its compatible with the 7641. I can see the other devices all have
	30	similar/same Harris markings in the bottom left of the IC obscured by the labels.
31	31
32		*** Note that the label for the 7643 PROM at IC25 was almost scraped off, but by its position
33		in the sequence, it has to be 6H. I removed a little more of the label in order to
34		work out what the inking was on it below, turned out to be 'D-2'. the prom at IC22 also
35		looks like it has an inked number under the paper label, just peeking through on one side.
36		Without removing the paper labels entirely, these markings wont be fully known, but were
37		covered for some reason.
	32	*** Note that the label for the 7643 PROM at IC25 was almost scraped off, but by its position
	33	in the sequence, it has to be 6H. I removed a little more of the label in order to
	34	work out what the inking was on it below, turned out to be 'D-2'. the prom at IC22 also
	35	looks like it has an inked number under the paper label, just peeking through on one side.
	36	Without removing the paper labels entirely, these markings wont be fully known, but were
	37	covered for some reason.
38	38
39		SPECS:
	39	SPECS:
40	40
41		- CPU is an NEC D8085A
42		- Crystal is marked 6.1440, but this looks to have been replaced.
43		- X1/X2 clock frequency measured at pins 1 + 2 is 6.14330 mhz
44		- Test point with stable readings is :
45		- TP4 (HS) = 15.9982 khz (Horizontal sync)
46		- TP5 (VS) = 60.5992 hz (Vertical Sync)
	41	- CPU is an NEC D8085A
	42	- Crystal is marked 6.1440, but this looks to have been replaced.
	43	- X1/X2 clock frequency measured at pins 1 + 2 is 6.14330 mhz
	44	- Test point with stable readings is :
	45	- TP4 (HS) = 15.9982 khz (Horizontal sync)
	46	- TP5 (VS) = 60.5992 hz (Vertical Sync)
47	47
48	48	***************************************************************************/
49	49
r248551	r248552
270	270
271	271	static MACHINE_CONFIG_START( mmagic, mmagic_state )
272	272	// basic machine hardware
273		MCFG_CPU_ADD("maincpu", I8085A, XTAL_6_144MHz) // NEC D8085A
	273	MCFG_CPU_ADD("maincpu", I8085A, XTAL_6_144MHz) // NEC D8085A
274	274	MCFG_CPU_PROGRAM_MAP(mmagic_mem)
275	275	MCFG_CPU_IO_MAP(mmagic_io)
276	276

trunk/src/mame/drivers/model3.c
r248551	r248552
6062	6062
6063	6063	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
6064	6064	#pragma GCC diagnostic pop
6065		#endif
		No newline at end of file
	6065	#endif

trunk/src/mame/drivers/namcona1.c
r248551	r248552
694	694	m_maskrom = (UINT16 *)memregion("maskrom")->base();
695	695	m_mEnableInterrupts = 0;
696	696	m_c140->set_base(m_workram);
697
	697
698	698	save_item(NAME(m_mEnableInterrupts));
699	699	save_item(NAME(m_count));
700	700	save_item(NAME(m_mcu_mailbox));

trunk/src/mame/drivers/naomi.c
r248551	r248552
1422	1422	XC9536 - Xilinx XC9536XL in-system programmable CPLD (PLCC44), stamped JULIE_DEV
1423	1423	XC2S30 - Xilinx XC2S30 Spartan-II FPGA (TQFP144), Rumble Fish 2 have printed sticker A08
1424	1424	17S30 - Xilinx 17S30APC OTP Configuration PROM, stamped SXFLS
1425		IC12-IC27 - Fujitsu MBM29DL640E 64M TSOP48 flash ROMs
	1425	IC12-IC27 - Fujitsu MBM29DL640E 64M TSOP48 flash ROMs
1426	1426
1427	1427
1428	1428	Network Board
r248551	r248552
9388	9388	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
9389	9389	#pragma GCC diagnostic pop
9390	9390	#endif
9391

trunk/src/mame/drivers/naughtyb.c
r248551	r248552
832	832	m_maincpu->space(AS_PROGRAM).install_read_handler(0x9090, 0x9090, read8_delegate(FUNC(naughtyb_state::popflame_protection_r),this));
833	833
834	834	m_maincpu->space(AS_PROGRAM).install_write_handler(0xb000, 0xb0ff, write8_delegate(FUNC(naughtyb_state::popflame_protection_w),this));
835
	835
836	836	save_item(NAME(m_popflame_prot_seed));
837	837	save_item(NAME(m_r_index));
838	838	save_item(NAME(m_prot_count));
r248551	r248552
864	864	{
865	865	/* install questions' handlers */
866	866	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc000, 0xc002, read8_delegate(FUNC(naughtyb_state::trvmstr_questions_r),this), write8_delegate(FUNC(naughtyb_state::trvmstr_questions_w),this));
867
	867
868	868	save_item(NAME(m_question_offset));
869	869	}
870	870

trunk/src/mame/drivers/nbmj9195.c
r248551	r248552
32	32	void nbmj9195_state::machine_start()
33	33	{
34	34	membank("soundbank")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x8000, 0x8000);
35
	35
36	36	save_item(NAME(m_inputport));
37	37	save_item(NAME(m_dipswbitsel));
38	38	save_item(NAME(m_outcoin_flag));

trunk/src/mame/drivers/nycaptor.c
r248551	r248552
743	743	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
744	744	else
745	745	membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x4000);
746
	746
747	747	save_item(NAME(m_generic_control_reg));
748	748	save_item(NAME(m_sound_nmi_enable));
749	749	save_item(NAME(m_pending_nmi));

trunk/src/mame/drivers/pcktgal.c
r248551	r248552
212	212	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x4000, 0xc000);
213	213	membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x6000, 0xc000);
214	214	membank("bank3")->configure_entries(0, 2, memregion("audiocpu")->base() + 0x10000, 0x4000);
215
	215
216	216	save_item(NAME(m_msm5205next));
217	217	save_item(NAME(m_toggle));
218	218	}

trunk/src/mame/drivers/photon2.c
r248551	r248552
105	105	{
106	106	m_spectrum_frame_number = 0;
107	107	m_spectrum_flash_invert = 0;
108
	108
109	109	save_item(NAME(m_spectrum_frame_number));
110	110	save_item(NAME(m_spectrum_flash_invert));
111	111	save_item(NAME(m_spectrum_port_fe));
r248551	r248552
329	329	{
330	330	membank("mainbank")->configure_entries(0, 4, memregion("maincpu")->base(), 0x4000);
331	331	membank("mainbank")->set_entry(0);
332
	332
333	333	save_item(NAME(m_nmi_enable));
334	334	}
335	335

trunk/src/mame/drivers/poolshrk.c
r248551	r248552
41	41	pSprite += 4;
42	42	}
43	43	}
44
	44
45	45	save_item(NAME(m_da_latch));
46	46	}
47	47

trunk/src/mame/drivers/rainbow.c
r248551	r248552
724	724	static MACHINE_CONFIG_DERIVED( jumpingi, jumping )
725	725	MCFG_CPU_REPLACE("maincpu", M68000, XTAL_16MHz/2) /* verified on pcb */
726	726	MCFG_CPU_PROGRAM_MAP(jumping_map)
727		MCFG_CPU_VBLANK_INT_DRIVER("screen", rbisland_state, irq4_line_hold)
	727	MCFG_CPU_VBLANK_INT_DRIVER("screen", rbisland_state, irq4_line_hold)
728	728	MACHINE_CONFIG_END
729	729
730	730	/***************************************************************************
r248551	r248552
902	902
903	903	/* red 'Imnoe' PCB */
904	904	ROM_START( jumpingi )
905		ROM_REGION( 0xa0000, "maincpu", 0 )
906		ROM_LOAD16_BYTE( "05.IC3", 0x00000, 0x20000, CRC(69ac4af4) SHA1(39055573e412e2591f7a68f9fee5919528529544) )
907		ROM_LOAD16_BYTE( "03.IC6", 0x00001, 0x20000, CRC(38975cdc) SHA1(23c02a4574a95904805d5f458c06c77c14d11c14) )
908		ROM_LOAD16_BYTE( "06.IC2", 0x40000, 0x20000, CRC(3ebb0fb8) SHA1(1b41b305623d121255eb70cb992e4d9da13abd82) ) // b22-03.23
909		ROM_LOAD16_BYTE( "04.IC5", 0x40001, 0x20000, CRC(91625e7f) SHA1(765afd973d9b82bb496b04beca284bf2769d6e6f) ) // b22-04.24
910		ROM_LOAD16_BYTE( "02", 0x80001, 0x10000, CRC(0810d327) SHA1(fe91ac02e617bde413dc8a20b7cbcaf3e20aeb28) ) /* c-chip substitute */
	905	ROM_REGION( 0xa0000, "maincpu", 0 )
	906	ROM_LOAD16_BYTE( "05.IC3", 0x00000, 0x20000, CRC(69ac4af4) SHA1(39055573e412e2591f7a68f9fee5919528529544) )
	907	ROM_LOAD16_BYTE( "03.IC6", 0x00001, 0x20000, CRC(38975cdc) SHA1(23c02a4574a95904805d5f458c06c77c14d11c14) )
	908	ROM_LOAD16_BYTE( "06.IC2", 0x40000, 0x20000, CRC(3ebb0fb8) SHA1(1b41b305623d121255eb70cb992e4d9da13abd82) ) // b22-03.23
	909	ROM_LOAD16_BYTE( "04.IC5", 0x40001, 0x20000, CRC(91625e7f) SHA1(765afd973d9b82bb496b04beca284bf2769d6e6f) ) // b22-04.24
	910	ROM_LOAD16_BYTE( "02", 0x80001, 0x10000, CRC(0810d327) SHA1(fe91ac02e617bde413dc8a20b7cbcaf3e20aeb28) ) /* c-chip substitute */
911	911
912		ROM_REGION( 0x14000, "audiocpu", 0 )
913		ROM_LOAD( "01.IC53", 0x00000, 0x8000, CRC(8527c00e) SHA1(86e3824caca39aca4ca4df63bb4474adacfc4c53) )
914		ROM_CONTINUE( 0x10000, 0x4000 )
915		ROM_CONTINUE( 0x0c000, 0x4000 )
	912	ROM_REGION( 0x14000, "audiocpu", 0 )
	913	ROM_LOAD( "01.IC53", 0x00000, 0x8000, CRC(8527c00e) SHA1(86e3824caca39aca4ca4df63bb4474adacfc4c53) )
	914	ROM_CONTINUE( 0x10000, 0x4000 )
	915	ROM_CONTINUE( 0x0c000, 0x4000 )
916	916
917		ROM_REGION( 0x80000, "gfx1", 0 )
918		ROM_LOAD( "13.IC8", 0x00000, 0x10000, CRC(65b76309) SHA1(1e345726e137f4c56d4bf239651c986fd53a16c3) ) /* tiles */
919		ROM_LOAD( "14.IC7", 0x10000, 0x10000, CRC(43a94283) SHA1(d6a05cbc7b996a8e7f1520563f6fada9a59021a4) )
920		ROM_LOAD( "11.IC10", 0x20000, 0x10000, CRC(e61933fb) SHA1(02bc0e1a7a3ce9e15fb83b28ce8fafb0b8d80ebd) )
921		ROM_LOAD( "12.IC9", 0x30000, 0x10000, CRC(ed031eb2) SHA1(905be4d890ff7bb8a4d8ad85b2a11483fb4d67eb) )
922		ROM_LOAD( "09.IC12", 0x40000, 0x10000, CRC(312700ca) SHA1(c79edc9c25f364d0afd79aaa21cfe2fe46044314) )
923		ROM_LOAD( "10.IC11", 0x50000, 0x10000, CRC(de3b0b88) SHA1(14b8871821e4c0abbb9967c5aa282cf4e67884fe) )
924		ROM_LOAD( "07.IC14", 0x60000, 0x10000, CRC(9fdc6c8e) SHA1(ff4e1a98dc982bce2f9d235cac62c7166f477f64) )
925		ROM_LOAD( "08.IC13", 0x70000, 0x10000, CRC(06226492) SHA1(834280ec49e61a0c9c6b6fe2033e1b20bd1bffbf) )
	917	ROM_REGION( 0x80000, "gfx1", 0 )
	918	ROM_LOAD( "13.IC8", 0x00000, 0x10000, CRC(65b76309) SHA1(1e345726e137f4c56d4bf239651c986fd53a16c3) ) /* tiles */
	919	ROM_LOAD( "14.IC7", 0x10000, 0x10000, CRC(43a94283) SHA1(d6a05cbc7b996a8e7f1520563f6fada9a59021a4) )
	920	ROM_LOAD( "11.IC10", 0x20000, 0x10000, CRC(e61933fb) SHA1(02bc0e1a7a3ce9e15fb83b28ce8fafb0b8d80ebd) )
	921	ROM_LOAD( "12.IC9", 0x30000, 0x10000, CRC(ed031eb2) SHA1(905be4d890ff7bb8a4d8ad85b2a11483fb4d67eb) )
	922	ROM_LOAD( "09.IC12", 0x40000, 0x10000, CRC(312700ca) SHA1(c79edc9c25f364d0afd79aaa21cfe2fe46044314) )
	923	ROM_LOAD( "10.IC11", 0x50000, 0x10000, CRC(de3b0b88) SHA1(14b8871821e4c0abbb9967c5aa282cf4e67884fe) )
	924	ROM_LOAD( "07.IC14", 0x60000, 0x10000, CRC(9fdc6c8e) SHA1(ff4e1a98dc982bce2f9d235cac62c7166f477f64) )
	925	ROM_LOAD( "08.IC13", 0x70000, 0x10000, CRC(06226492) SHA1(834280ec49e61a0c9c6b6fe2033e1b20bd1bffbf) )
926	926
927		ROM_REGION( 0xa0000, "gfx2", ROMREGION_INVERT )
928		ROM_LOAD( "15.IC62", 0x00000, 0x10000, CRC(8548db6c) SHA1(675cd301259d5ed16098a38ac58b27b5ccd91264) ) /* sprites */
929		ROM_LOAD( "19.IC61", 0x10000, 0x10000, CRC(89b3d8ee) SHA1(8491de6e8292e58b9a8696be15827bcb1ea42845) )
930		ROM_LOAD( "23.IC60", 0x20000, 0x08000, CRC(662a2f1e) SHA1(1c5e8b1f0623e64faf9cd60f9653fc5957191a9b) )
931		ROM_LOAD( "16.IC78", 0x28000, 0x10000, CRC(925865e1) SHA1(457de50bc03e8b949ac7d46ae4188201e87574a8) )
932		ROM_LOAD( "20.IC77", 0x38000, 0x10000, CRC(b09695d1) SHA1(e6d315f9befb7b47f42668d573a1102e52d78aea) )
933		ROM_LOAD( "24.IC76", 0x48000, 0x08000, CRC(41937743) SHA1(890c832a7cf87e6fe749d4824b02d57e10872bdf) )
934		ROM_LOAD( "17.IC93", 0x50000, 0x10000, CRC(f644eeab) SHA1(9d45e9dfb08e8c90b4b10f5dc383fa4732161a81) )
935		ROM_LOAD( "21.IC92", 0x60000, 0x10000, CRC(16e1b0ff) SHA1(1467a317d07a447d01113e6b6b9f5aca30cb0dcb) )
936		ROM_LOAD( "25.IC91", 0x70000, 0x08000, CRC(d886c014) SHA1(9327c332c98a81451e9e0624344d2601ef06e490) )
937		ROM_LOAD( "18.IC121", 0x78000, 0x10000, CRC(93df1e4d) SHA1(b100d265b973254ec9cd44b6c32f62b4bac3b732) )
938		ROM_LOAD( "22.IC120", 0x88000, 0x10000, CRC(7c4e893b) SHA1(eceecb38554157ee24d228a2c722dad750a6a07d) )
939		ROM_LOAD( "26.IC119", 0x98000, 0x08000, CRC(7e1d58d8) SHA1(d586a018c3ec3e6e6a39992170d324361e03c68a) )
	927	ROM_REGION( 0xa0000, "gfx2", ROMREGION_INVERT )
	928	ROM_LOAD( "15.IC62", 0x00000, 0x10000, CRC(8548db6c) SHA1(675cd301259d5ed16098a38ac58b27b5ccd91264) ) /* sprites */
	929	ROM_LOAD( "19.IC61", 0x10000, 0x10000, CRC(89b3d8ee) SHA1(8491de6e8292e58b9a8696be15827bcb1ea42845) )
	930	ROM_LOAD( "23.IC60", 0x20000, 0x08000, CRC(662a2f1e) SHA1(1c5e8b1f0623e64faf9cd60f9653fc5957191a9b) )
	931	ROM_LOAD( "16.IC78", 0x28000, 0x10000, CRC(925865e1) SHA1(457de50bc03e8b949ac7d46ae4188201e87574a8) )
	932	ROM_LOAD( "20.IC77", 0x38000, 0x10000, CRC(b09695d1) SHA1(e6d315f9befb7b47f42668d573a1102e52d78aea) )
	933	ROM_LOAD( "24.IC76", 0x48000, 0x08000, CRC(41937743) SHA1(890c832a7cf87e6fe749d4824b02d57e10872bdf) )
	934	ROM_LOAD( "17.IC93", 0x50000, 0x10000, CRC(f644eeab) SHA1(9d45e9dfb08e8c90b4b10f5dc383fa4732161a81) )
	935	ROM_LOAD( "21.IC92", 0x60000, 0x10000, CRC(16e1b0ff) SHA1(1467a317d07a447d01113e6b6b9f5aca30cb0dcb) )
	936	ROM_LOAD( "25.IC91", 0x70000, 0x08000, CRC(d886c014) SHA1(9327c332c98a81451e9e0624344d2601ef06e490) )
	937	ROM_LOAD( "18.IC121", 0x78000, 0x10000, CRC(93df1e4d) SHA1(b100d265b973254ec9cd44b6c32f62b4bac3b732) )
	938	ROM_LOAD( "22.IC120", 0x88000, 0x10000, CRC(7c4e893b) SHA1(eceecb38554157ee24d228a2c722dad750a6a07d) )
	939	ROM_LOAD( "26.IC119", 0x98000, 0x08000, CRC(7e1d58d8) SHA1(d586a018c3ec3e6e6a39992170d324361e03c68a) )
940	940
941		ROM_REGION( 0x200, "pals", 0 )
942		ROM_LOAD( "JP2.IC56", 0x000, 0x104, CRC(12e9a7b8) SHA1(a0ce8b6083c9adfcb4bdbca87f63a01f292525f3) ) // PAL16R6A-2CN
943		ROM_LOAD( "JP1.IC13", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) ) // PAL20L8A-2CNS
944		ROM_LOAD( "JP3.IC51", 0x000, 0x104, CRC(c1e6cb8f) SHA1(9908e62bb9b806047b7a344bb62334bd696b9fc8) ) // PAL16L8A-2CN z80 address decoder?
	941	ROM_REGION( 0x200, "pals", 0 )
	942	ROM_LOAD( "JP2.IC56", 0x000, 0x104, CRC(12e9a7b8) SHA1(a0ce8b6083c9adfcb4bdbca87f63a01f292525f3) ) // PAL16R6A-2CN
	943	ROM_LOAD( "JP1.IC13", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) ) // PAL20L8A-2CNS
	944	ROM_LOAD( "JP3.IC51", 0x000, 0x104, CRC(c1e6cb8f) SHA1(9908e62bb9b806047b7a344bb62334bd696b9fc8) ) // PAL16L8A-2CN z80 address decoder?
945	945	ROM_END
946	946
947	947	DRIVER_INIT_MEMBER(rbisland_state,rbisland)

trunk/src/mame/drivers/sbowling.c
r248551	r248552
100	100	y = 255-y;
101	101	x = 247-x;
102	102	}
103
	103
104	104	tmpbitmap->pix16(y, x) = col;
105	105	}
106	106

trunk/src/mame/drivers/segas32.c
r248551	r248552
2486	2486	MCFG_RF5C68_ADD("rfsnd", RFC_CLOCK/4)
2487	2487	MCFG_SOUND_ROUTE(0, "lspeaker", 0.55)
2488	2488	MCFG_SOUND_ROUTE(1, "rspeaker", 0.55)
2489
	2489
2490	2490	MCFG_S32COMM_ADD("s32comm")
2491	2491	MACHINE_CONFIG_END
2492	2492
r248551	r248552
2572	2572	MCFG_SOUND_ADD("sega", MULTIPCM, MASTER_CLOCK/4)
2573	2573	MCFG_SOUND_ROUTE(1, "lspeaker", 1.0)
2574	2574	MCFG_SOUND_ROUTE(0, "rspeaker", 1.0)
2575
	2575
2576	2576	MCFG_S32COMM_ADD("s32comm")
2577	2577	MACHINE_CONFIG_END
2578	2578
r248551	r248552
5237	5237	m_system32_prot_vblank = &segas32_state::f1lap_fd1149_vblank;
5238	5238
5239	5239	m_sw1_output = &segas32_state::f1lap_sw1_output;
5240
	5240
5241	5241	m_s32comm->set_linktype(15612); // EPR-15612
5242	5242	}
5243	5243
r248551	r248552
5303	5303	segas32_common_init(read16_delegate(FUNC(segas32_state::analog_custom_io_r),this), write16_delegate(FUNC(segas32_state::analog_custom_io_w),this));
5304	5304	m_sw1_output = &segas32_state::radm_sw1_output;
5305	5305	m_sw2_output = &segas32_state::radr_sw2_output;
5306
	5306
5307	5307	m_s32comm->set_linktype(14084); // EPR-14084
5308	5308	}
5309	5309

trunk/src/mame/drivers/segaybd.c
r248551	r248552
836	836
837	837	/*
838	838	static ADDRESS_MAP_START( motor_portmap, AS_IO, 8, segaybd_state )
839		ADDRESS_MAP_UNMAP_HIGH
840		ADDRESS_MAP_GLOBAL_MASK(0xff)
	839	ADDRESS_MAP_UNMAP_HIGH
	840	ADDRESS_MAP_GLOBAL_MASK(0xff)
841	841	ADDRESS_MAP_END
842	842	*/
843	843
r248551	r248552
1440	1440	// basic machine hardware
1441	1441	MCFG_CPU_ADD("motorcpu", Z80, XTAL_16MHz/2 ) // 8 Mhz(guessed)
1442	1442	MCFG_CPU_PROGRAM_MAP(motor_map)
1443		// MCFG_CPU_IO_MAP(motor_portmap)
	1443	// MCFG_CPU_IO_MAP(motor_portmap)
1444	1444
1445	1445	MACHINE_CONFIG_END
1446	1446

trunk/src/mame/drivers/silvmil.c
r248551	r248552
446	446	MACHINE_CONFIG_END
447	447
448	448	static MACHINE_CONFIG_DERIVED( puzzlovek, puzzlove )
449		MCFG_DEVICE_REMOVE("ymsnd")
450		MCFG_YM2151_ADD("ymsnd", XTAL_15MHz/4) /* Verified */
451		MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
452		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
	449	MCFG_DEVICE_REMOVE("ymsnd")
	450	MCFG_YM2151_ADD("ymsnd", XTAL_15MHz/4) /* Verified */
	451	MCFG_YM2151_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
	452	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
453	453	MACHINE_CONFIG_END
454	454
455	455
r248551	r248552
587	587	tumblepb_gfx1_rearrange();
588	588	}
589	589
590		GAME( 1995, silvmil, 0, silvmil, silvmil, silvmil_state, silvmil, ROT270, "Para", "Silver Millennium", GAME_SUPPORTS_SAVE )
591		GAME( 1994, puzzlove, 0, puzzlove, puzzlove, silvmil_state, silvmil, ROT0, "Para", "PuzzLove", GAME_SUPPORTS_SAVE )
592		GAME( 1994, puzzlovek, puzzlove, puzzlovek, puzzlovek, silvmil_state, silvmil, ROT0, "Para", "PuzzLove (Korea)", GAME_SUPPORTS_SAVE )
	590	GAME( 1995, silvmil, 0, silvmil, silvmil, silvmil_state, silvmil, ROT270, "Para", "Silver Millennium", GAME_SUPPORTS_SAVE )
	591	GAME( 1994, puzzlove, 0, puzzlove, puzzlove, silvmil_state, silvmil, ROT0, "Para", "PuzzLove", GAME_SUPPORTS_SAVE )
	592	GAME( 1994, puzzlovek, puzzlove, puzzlovek, puzzlovek, silvmil_state, silvmil, ROT0, "Para", "PuzzLove (Korea)", GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/suna8.c
r248551	r248552
1918	1918	MCFG_CPU_ADD("maincpu", Z80, SUNA8_MASTER_CLOCK / 4) /* ? */
1919	1919	MCFG_CPU_PROGRAM_MAP(rranger_map)
1920	1920	MCFG_CPU_IO_MAP(rranger_io_map)
1921		// MCFG_CPU_DECRYPTED_OPCODES_MAP(decrypted_opcodes_map)
	1921	// MCFG_CPU_DECRYPTED_OPCODES_MAP(decrypted_opcodes_map)
1922	1922	MCFG_CPU_VBLANK_INT_DRIVER("screen", suna8_state, irq0_line_hold) /* IRQ & NMI ! */
1923	1923
1924	1924	MCFG_CPU_ADD("audiocpu", Z80, SUNA8_MASTER_CLOCK / 8) /* verified on pcb */

trunk/src/mame/drivers/system1.c
r248551	r248552
129	129
130	130	834-5583-12 SPATTER (sticker)
131	131	834-5542 daughter board with 4 eproms (EPR6306, EPR6307, EPR6308, EPR6309)
132		834-5540 daughter board with logic ICs
	132	834-5540 daughter board with logic ICs
133	133	315-5099 custom Z80 CPU w/security
134	134
135	135	*******************************************************************************
r248551	r248552
380	380	m_bank1->set_entry(0);
381	381
382	382	if (m_banked_decrypted_opcodes)
383		{
	383	{
384	384	m_bank0d->set_base(m_banked_decrypted_opcodes);
385	385	m_bank1d->configure_entries(0, numbanks, m_banked_decrypted_opcodes + 0x10000, 0x4000);
386	386	m_bank1d->set_entry(0);
r248551	r248552
2821	2821
2822	2822	ROM_START( spattera )
2823	2823	ROM_REGION( 0x10000, "maincpu", 0 )
2824		ROM_LOAD( "epr-6597.116", 0x0000, 0x4000, CRC(fb928b9d) SHA1(0a9bede7a147009b9ebb8a0b73681359da665982) ) /* encrypted */
	2824	ROM_LOAD( "epr-6597.116", 0x0000, 0x4000, CRC(fb928b9d) SHA1(0a9bede7a147009b9ebb8a0b73681359da665982) ) /* encrypted */
2825	2825	ROM_LOAD( "epr-6598.109", 0x4000, 0x4000, CRC(5dff037a) SHA1(8e6f6b75a89609ab0498d317c11e6d653343ffbe) ) /* encrypted */
2826	2826	ROM_LOAD( "epr-6599.96", 0x8000, 0x4000, CRC(7ba9de5b) SHA1(f18542c95e8241433ed995c213924ad1ce03cd5b) )
2827	2827

trunk/src/mame/drivers/system16.c
r248551	r248552
137	137	AM_RANGE(0x412000, 0x412fff) AM_RAM AM_SHARE("bg1_tileram")
138	138	AM_RANGE(0x440000, 0x440fff) AM_RAM AM_SHARE("sprites")
139	139	AM_RANGE(0x840000, 0x840fff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
140		// AM_RANGE(0xc40000, 0xc40001) AM_WRITE(sound_command_irq_w)
	140	// AM_RANGE(0xc40000, 0xc40001) AM_WRITE(sound_command_irq_w)
141	141	AM_RANGE(0xC42006, 0xC42007) AM_WRITE(sound_command_irq_w)
142
	142
143	143	AM_RANGE(0xC44000, 0xC44001) AM_READNOP
144	144	AM_RANGE(0xc41000, 0xc41001) AM_READ_PORT("SERVICE")
145	145	AM_RANGE(0xc41002, 0xc41003) AM_READ_PORT("P1")
r248551	r248552
2133	2133
2134	2134	// 2x YM2203C, one at U57, one at U56
2135	2135	MCFG_SOUND_ADD("ym1", YM2203, 4000000)
2136		// MCFG_YM2203_IRQ_HANDLER(WRITELINE(segas1x_bootleg_state, datsu_irq_handler))
	2136	// MCFG_YM2203_IRQ_HANDLER(WRITELINE(segas1x_bootleg_state, datsu_irq_handler))
2137	2137	MCFG_SOUND_ROUTE(0, "mono", 0.50)
2138	2138	MCFG_SOUND_ROUTE(1, "mono", 0.50)
2139	2139	MCFG_SOUND_ROUTE(2, "mono", 0.50)
r248551	r248552
2141	2141
2142	2142	MCFG_SOUND_ADD("ym2", YM2203, 4000000)
2143	2143	MCFG_SOUND_ROUTE(0, "mono", 0.50)
2144		// MCFG_YM2203_IRQ_HANDLER(WRITELINE(segas1x_bootleg_state, datsu_irq_handler))
	2144	// MCFG_YM2203_IRQ_HANDLER(WRITELINE(segas1x_bootleg_state, datsu_irq_handler))
2145	2145	MCFG_SOUND_ROUTE(1, "mono", 0.50)
2146	2146	MCFG_SOUND_ROUTE(2, "mono", 0.50)
2147	2147	MCFG_SOUND_ROUTE(3, "mono", 0.80)

trunk/src/mame/drivers/taitoair.c
r248551	r248552
186	186	/*!
187	187	@todo - Framebuffer DMA requires palette switch to be selected dynamically, see at first stage Course Select in Top Landing.
188	188	My gut feeling is that 3d poly fill operation actually copies to internal buffer then a DMA op actually do the buffer-to-screen copy, including gradiation ROZ too;
189		- Air Inferno: missing landing monitor camera (blackened);
190		- Air Inferno: missing 3d HUD graphics;
191		- Air Inferno: Expert course has wrong 3d geometry;
192		- Air Inferno: Almost surely crashing during replay has missing smoke effect, looks quite odd atm.
193		- Top Landing: Night stages might have wrong priority for stars-above-sea;
194		- Input limiters / analog thresholds for both games;
	189	- Air Inferno: missing landing monitor camera (blackened);
	190	- Air Inferno: missing 3d HUD graphics;
	191	- Air Inferno: Expert course has wrong 3d geometry;
	192	- Air Inferno: Almost surely crashing during replay has missing smoke effect, looks quite odd atm.
	193	- Top Landing: Night stages might have wrong priority for stars-above-sea;
	194	- Input limiters / analog thresholds for both games;
195	195	*/
196	196
197	197	#include "emu.h"
r248551	r248552
344	344	}
345	345
346	346	/*!
347		@brief Framebuffer DMA control
348		@regs [0] x--- ---- ---- ---- copy framebuffer to the screen
349		[0] --x- ---- ---- ---- unknown, used on POST test
350		[0] 1001 1111 1111 1111 used by Air Inferno after erase op, erase -> copy?
351		[0] 0001 1111 1111 1111 erase op?
352		[1] xxxx xxxx xxxx xxxx fill value? 0xffff by Top Landing, 0x0000 Air Inferno
353		[2] (unused)
354		[3] both games uses 0xb7, most likely a register setting.
	347	@brief Framebuffer DMA control
	348	@regs [0] x--- ---- ---- ---- copy framebuffer to the screen
	349	[0] --x- ---- ---- ---- unknown, used on POST test
	350	[0] 1001 1111 1111 1111 used by Air Inferno after erase op, erase -> copy?
	351	[0] 0001 1111 1111 1111 erase op?
	352	[1] xxxx xxxx xxxx xxxx fill value? 0xffff by Top Landing, 0x0000 Air Inferno
	353	[2] (unused)
	354	[3] both games uses 0xb7, most likely a register setting.
355	355	*/
356	356	WRITE16_MEMBER(taitoair_state::dma_regs_w)
357	357	{

trunk/src/mame/drivers/thedealr.c
r248551	r248552
4	4
5	5	The Dealer (Visco Games)
6	6
7		Driver by Luca Elia
8		This game runs on Seta Hardware
	7	Driver by Luca Elia
	8	This game runs on Seta Hardware
9	9
10	10	P0-040A PCB:
11	11
r248551	r248552
94	94	{
95	95	bitmap.fill(0x1f0, cliprect);
96	96
97		m_seta001->set_bg_yoffsets( 0x11+1, -0x10 ); // + is up (down with flip)
	97	m_seta001->set_bg_yoffsets( 0x11+1, -0x10 ); // + is up (down with flip)
98	98	m_seta001->set_fg_yoffsets( -0x12+1, -0x01 );
99	99
100	100	m_seta001->draw_sprites(screen, bitmap, cliprect, 0x1000, 1);
r248551	r248552
120	120
121	121	void thedealr_state::iox_reset()
122	122	{
123		m_iox_status = 0x00;
124		m_iox_ret = 0x00;
125		m_iox_cmd = 0xff;
126		m_iox_leds = 0x00;
127		m_iox_coins = 0x00;
	123	m_iox_status = 0x00;
	124	m_iox_ret = 0x00;
	125	m_iox_cmd = 0xff;
	126	m_iox_leds = 0x00;
	127	m_iox_coins = 0x00;
128	128	}
129	129
130	130	MACHINE_RESET_MEMBER(thedealr_state,thedealr)
r248551	r248552
150	150
151	151	switch (m_iox_cmd)
152	152	{
153		case 0x20: // leds
	153	case 0x20: // leds
154	154	m_iox_leds = data;
155		set_led_status(machine(), 0, data & 0x01); // bet
156		set_led_status(machine(), 1, data & 0x02); // deal
	155	set_led_status(machine(), 0, data & 0x01); // bet
	156	set_led_status(machine(), 1, data & 0x02); // deal
157	157	set_led_status(machine(), 2, data & 0x04);
158	158	set_led_status(machine(), 3, data & 0x08);
159		set_led_status(machine(), 4, data & 0x10); // hold 1-5?
	159	set_led_status(machine(), 4, data & 0x10); // hold 1-5?
160	160	set_led_status(machine(), 5, data & 0x20);
161	161	set_led_status(machine(), 6, data & 0x40);
162	162	set_led_status(machine(), 7, data & 0x80);
163	163	break;
164	164
165		case 0x40: // coin counters
	165	case 0x40: // coin counters
166	166	m_iox_coins = data;
167	167	coin_counter_w(machine(), 0, (~data) & 0x02); // coin1 or service coin
168	168	coin_counter_w(machine(), 1, (~data) & 0x04); // coupon
r248551	r248552
177	177	break;
178	178	}
179	179
180		// popmessage("LED: %02X COIN: %02X", m_iox_leds, m_iox_coins);
	180	// popmessage("LED: %02X COIN: %02X", m_iox_leds, m_iox_coins);
181	181	}
182	182	else
183	183	{
r248551	r248552
186	186
187	187	switch (m_iox_cmd)
188	188	{
189		case 0x01: // inputs?
	189	case 0x01: // inputs?
190	190	{
191	191	UINT16 buttons = ioport("IOX")->read();
192	192	m_iox_ret = 0;
r248551	r248552
202	202	break;
203	203	}
204	204
205		// case 0x04: // ? at boot
	205	// case 0x04: // ? at boot
206	206
207		case 0x08: // return iox version
	207	case 0x08: // return iox version
208	208	m_iox_ret = 0x54;
209	209	m_iox_status \|= IOX_OUT_FULL;
210	210	break;
211	211
212		case 0x20: // leds
	212	case 0x20: // leds
213	213	m_iox_status \|= IOX_WAITDATA;
214	214	break;
215	215
216		case 0x40: // coin counters
	216	case 0x40: // coin counters
217	217	m_iox_status \|= IOX_WAITDATA;
218	218	break;
219	219
220		case 0x80: // store param?
	220	case 0x80: // store param?
221	221	m_iox_status \|= IOX_WAITDATA;
222	222	break;
223	223
224		case 0x81: // store param?
	224	case 0x81: // store param?
225	225	m_iox_status \|= IOX_WAITDATA;
226	226	break;
227	227
228		case 0xff: // reset
	228	case 0xff: // reset
229	229	iox_reset();
230	230	break;
231	231
r248551	r248552
262	262	// bit 2 - ? 0 during game
263	263	// bit 3 - ? 1 during game
264	264	// bit 7 - ? 0 during game
265		// popmessage("UNK %02x", data);
	265	// popmessage("UNK %02x", data);
266	266	}
267	267
268	268	static ADDRESS_MAP_START( thedealr, AS_PROGRAM, 8, thedealr_state )
269	269	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")
270	270
271		AM_RANGE(0x2000, 0x2000) AM_RAM // w ff at boot (after clearing commram)
	271	AM_RANGE(0x2000, 0x2000) AM_RAM // w ff at boot (after clearing commram)
272	272
273		AM_RANGE(0x2400, 0x2400) AM_READ(irq_ack_r) // r = irq ack.
274		AM_RANGE(0x2400, 0x2400) AM_WRITE(unk_w) // w = ?
	273	AM_RANGE(0x2400, 0x2400) AM_READ(irq_ack_r) // r = irq ack.
	274	AM_RANGE(0x2400, 0x2400) AM_WRITE(unk_w) // w = ?
275	275
276		AM_RANGE(0x2800, 0x2800) AM_READ_PORT("COINS") AM_WRITENOP // rw
	276	AM_RANGE(0x2800, 0x2800) AM_READ_PORT("COINS") AM_WRITENOP // rw
277	277
278	278	AM_RANGE(0x2801, 0x2801) AM_READ_PORT("DSW4")
279	279	AM_RANGE(0x2c00, 0x2c00) AM_READ_PORT("DSW3")
r248551	r248552
281	281	AM_RANGE(0x3400, 0x3400) AM_READWRITE(iox_r, iox_w)
282	282	AM_RANGE(0x3401, 0x3401) AM_READ(iox_status_r)
283	283
284		AM_RANGE(0x3000, 0x3000) AM_RAM // rw, comm in test mode
285		AM_RANGE(0x3001, 0x3001) AM_RAM // rw, ""
	284	AM_RANGE(0x3000, 0x3000) AM_RAM // rw, comm in test mode
	285	AM_RANGE(0x3001, 0x3001) AM_RAM // rw, ""
286	286
287	287	AM_RANGE(0x3800, 0x3bff) AM_RAM AM_SHARE("commram")
288	288
r248551	r248552
375	375	Switches 7 & 8 control the payout as follows:
376	376
377	377	Off/Off Off/On On/Off On/On Notes
378		---------------------------------------------------------------------------------------------
	378	---------------------------------------------------------------------------------------------
379	379	Jackpot MB 5000 5000 5000 2000 Ryl Flush bonus at Max Bet
380	380	Jackpot 2500 2500 2500 1000 Ryl Flush bonus at 5 coins + 500 (or 200) per coin up to Max Bet
381	381	Mini JP 1500 1500 1000 500 Str Flush bonus at Max Bet
r248551	r248552
444	444	3 of a Kind winning hand Jacks or higher enters Fever Mode
445	445	You start with a pair of your 3 of a Kind cards & you draw 3 cards each hand.
446	446	Jacks through Kings get 5 Fever Mode Draws
447		Aces get 15 Fever Mode Draws
	447	Aces get 15 Fever Mode Draws
448	448	*/
449	449	PORT_DIPNAME( 0x20, 0x20, "Fever Mode" ) PORT_DIPLOCATION("SW3:6")
450	450	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
r248551	r248552
455	455	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
456	456
457	457	PORT_START("DSW4")
458		PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW4:7" ) // X in service mode
459		PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW4:8" ) // ""
	458	PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW4:7" ) // X in service mode
	459	PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW4:8" ) // ""
460	460	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW4:1")
461	461	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
462	462	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
463		PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW4:2" ) // "Excess switch time" error
	463	PORT_DIPUNKNOWN_DIPLOC( 0x08, 0x08, "SW4:2" ) // "Excess switch time" error
464	464	PORT_DIPUNKNOWN_DIPLOC( 0x10, 0x10, "SW4:3" )
465	465	PORT_DIPUNKNOWN_DIPLOC( 0x20, 0x20, "SW4:4" )
466	466	PORT_DIPUNKNOWN_DIPLOC( 0x40, 0x40, "SW4:5" )
r248551	r248552
522	522	static MACHINE_CONFIG_START( thedealr, thedealr_state )
523	523
524	524	// basic machine hardware
525		MCFG_CPU_ADD("maincpu", R65C02, XTAL_16MHz/8) // 2 MHz?
	525	MCFG_CPU_ADD("maincpu", R65C02, XTAL_16MHz/8) // 2 MHz?
526	526	MCFG_CPU_PROGRAM_MAP(thedealr)
527	527	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", thedealr_state, thedealr_interrupt, "screen", 0, 1)
528	528
529		MCFG_CPU_ADD("subcpu", R65C02, XTAL_16MHz/8) // 2 MHz?
	529	MCFG_CPU_ADD("subcpu", R65C02, XTAL_16MHz/8) // 2 MHz?
530	530	MCFG_CPU_PROGRAM_MAP(thedealr_sub)
531	531	MCFG_CPU_VBLANK_INT_DRIVER("screen", thedealr_state, nmi_line_pulse)
532	532
r248551	r248552
555	555
556	556	// sound hardware
557	557	MCFG_SPEAKER_STANDARD_MONO("mono")
558		MCFG_SOUND_ADD("aysnd", YM2149, XTAL_16MHz/8) // 2 MHz?
	558	MCFG_SOUND_ADD("aysnd", YM2149, XTAL_16MHz/8) // 2 MHz?
559	559	MCFG_AY8910_PORT_A_READ_CB(IOPORT("DSW2"))
560	560	MCFG_AY8910_PORT_B_READ_CB(IOPORT("DSW1"))
561	561	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

trunk/src/mame/drivers/tnzs.c
r248551	r248552
2495	2495	ROM_LOAD( "b53-15.pal16l8a.subpcb.ic6.jed", 0x00000, 0x01000, NO_DUMP) // on sub pcb
2496	2496	ROM_END
2497	2497
2498		/* tnzs - old style PCB sets
	2498	/* tnzs - old style PCB sets
2499	2499	The New Zealand Story
2500	2500	Taito, 1988
2501	2501

trunk/src/mame/drivers/ttchamp.c
r248551	r248552
82	82
83	83	required_device<cpu_device> m_maincpu;
84	84	required_device<palette_device> m_palette;
85
	85
86	86	UINT16 m_paloff;
87	87	UINT16 m_port10;
88	88	UINT8 m_rombank;
r248551	r248552
155	155
156	156	m_bakram = auto_alloc_array(machine(), UINT8, 0x100);
157	157	machine().device<nvram_device>("backram")->set_base(m_bakram, 0x100);
158
	158
159	159	save_item(NAME(m_paloff));
160	160	save_item(NAME(m_port10));
161	161	save_item(NAME(m_rombank));

trunk/src/mame/drivers/turbo.c
r248551	r248552
1085	1085	ROM_START( turbob )
1086	1086	ROM_REGION( 0x6000, "maincpu", 0 )
1087	1087	// B revision label on 1st rom, A revision for 2nd / 3rd, 2nd rom was faulty, 3rd rom matched existing set, existing 2nd rom passes rom check.
1088		ROM_LOAD( "epr-1363_t5b.ic76", 0x0000, 0x2000, CRC(f7f28149) SHA1(08aec3edd6d756b14b2f10fe5abd22ac83c79fcc) ) /* CPU module stamped as 834-0128 */
1089		ROM_LOAD( "epr-1364_t5a.ic89", 0x2000, 0x2000, CRC(6a341693) SHA1(428927c4a14bf82225875012c255d25dcffaf2ab) )
1090		ROM_LOAD( "epr-1365_t5a.ic103", 0x4000, 0x2000, CRC(3b6b0dc8) SHA1(3ebfa3f9fabd444ee105591acb6984b6b3523725) )
	1088	ROM_LOAD( "epr-1363_t5b.ic76", 0x0000, 0x2000, CRC(f7f28149) SHA1(08aec3edd6d756b14b2f10fe5abd22ac83c79fcc) ) /* CPU module stamped as 834-0128 */
	1089	ROM_LOAD( "epr-1364_t5a.ic89", 0x2000, 0x2000, CRC(6a341693) SHA1(428927c4a14bf82225875012c255d25dcffaf2ab) )
	1090	ROM_LOAD( "epr-1365_t5a.ic103", 0x4000, 0x2000, CRC(3b6b0dc8) SHA1(3ebfa3f9fabd444ee105591acb6984b6b3523725) )
1091	1091
1092	1092	ROM_REGION( 0x20000, "sprites", 0 ) /* sprite data */
1093	1093	ROM_LOAD( "epr-1246.prom-ic84", 0x00000, 0x2000, CRC(555bfe9a) SHA1(1e56385475eeff044dcd9b44a154991d3efe995e) ) /* level 0 */
r248551	r248552
1192	1192
1193	1193	ROM_START( turbod )
1194	1194	ROM_REGION( 0x6000, "maincpu", 0 )
1195		// no letter on rom labels, numbered 1363-1365, possibly the original 1363-1365 revision? - service mode still shows the older EPR-1262 through EPR-1264 tho?
1196		ROM_LOAD( "1363.ic76", 0x0000, 0x2000, CRC(b6329a00) SHA1(02ca3d7703607bc0390a14d838fafb01a3e3cdef) ) /* CPU module stamped as 834-0128 */
	1195	// no letter on rom labels, numbered 1363-1365, possibly the original 1363-1365 revision? - service mode still shows the older EPR-1262 through EPR-1264 tho?
	1196	ROM_LOAD( "1363.ic76", 0x0000, 0x2000, CRC(b6329a00) SHA1(02ca3d7703607bc0390a14d838fafb01a3e3cdef) ) /* CPU module stamped as 834-0128 */
1197	1197	ROM_LOAD( "1364.ic89", 0x2000, 0x2000, CRC(3192f83b) SHA1(78dabb75e38f5f8331bfc43dce852a4c4397f874) )
1198	1198	ROM_LOAD( "1365.ic103", 0x4000, 0x2000, CRC(23a3303a) SHA1(bcc4ab9203060b4043d779b7a242abc583093dbb) )
1199	1199

trunk/src/mame/drivers/vegas.c
r248551	r248552
2537	2537
2538	2538	DISK_REGION( "ide:0:hdd:image" )
2539	2539	// various strings from this image
2540		// SHOWTIME REV 2.0
	2540	// SHOWTIME REV 2.0
2541	2541	// BUILD DATE: Apr 25 1999 (diag.exe?)
2542	2542	// BUILD DATE: Apr 21 1999 (game?)
2543	2543	DISK_IMAGE( "nbashowt", 0, SHA1(f7c56bc3dcbebc434de58034986179ae01127f87) )
r248551	r248552
2555	2555
2556	2556	DISK_REGION( "ide:0:hdd:image" )
2557	2557	// various strings from this image
2558		//NBA SHOWTIME 2.1
	2558	//NBA SHOWTIME 2.1
2559	2559	//BUILD DATE: Sep 22 1999 (diag.exe?)
2560	2560	//BUILD DATE: Sep 21 1999 (game?)
2561	2561	DISK_IMAGE( "nbanfl", 0, SHA1(f60c627f85f1bf58f2ea674063736a1e516e7e9e) )
r248551	r248552
2568	2568	// it's possible the boot rom and CHD are mismatched here
2569	2569	ROM_START( nbagold )
2570	2570	ROM_REGION32_LE( 0x80000, "user1", 0 )
2571		ROM_LOAD( "nbagold_jan10_2000.u27", 0x000000, 0x80000, CRC(6768e802) SHA1(d994e3efe14f57e261841134ddd1489fa67d418b) ) // 11:29:11 Jan 10 2000. BIOS FOR NBAGOLD USING BANSHEE / 11:23:58 Jan 10 2000. POST FOR NBAGOLD USING BANSHEE
	2571	ROM_LOAD( "nbagold_jan10_2000.u27", 0x000000, 0x80000, CRC(6768e802) SHA1(d994e3efe14f57e261841134ddd1489fa67d418b) ) // 11:29:11 Jan 10 2000. BIOS FOR NBAGOLD USING BANSHEE / 11:23:58 Jan 10 2000. POST FOR NBAGOLD USING BANSHEE
2572	2572
2573	2573	DISK_REGION( "ide:0:hdd:image" )
2574	2574	// various strings from this image
r248551	r248552
2578	2578	//BUILD DATE:Feb 10 2000 (something else?)
2579	2579	DISK_IMAGE( "nbanfl3", 0, SHA1(19a51346ce5ae4e06e8dff3eb4bed59ec1ee855f))
2580	2580	// these both contain the same strings / build dates, same thing with different user data / drive sizes?
2581		// DISK_IMAGE( "nbanfl27", 0, SHA1(da371d27e2fbceec493e2203055e0c1399eaf3b9) )
2582		// DISK_IMAGE( "sportstn", 0, SHA1(9442feefaeb5ae4a090422e937615f8a2d8e8f31) )
2583
	2581	// DISK_IMAGE( "nbanfl27", 0, SHA1(da371d27e2fbceec493e2203055e0c1399eaf3b9) )
	2582	// DISK_IMAGE( "sportstn", 0, SHA1(9442feefaeb5ae4a090422e937615f8a2d8e8f31) )
2584	2583
	2584
2585	2585	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* Vegas SIO boot ROM */
2586	2586	ROM_LOAD16_BYTE( "vegassio.bin", 0x000000, 0x8000, CRC(d1470e23) SHA1(f6e8405cfa604528c0224401bc374a6df9caccef) )
2587	2587

trunk/src/mame/drivers/xyonix.c
r248551	r248552
262	262
263	263	ROM_REGION( 0x10000, "mcu", 0 )
264	264	ROM_LOAD( "mc68705p3s.e7", 0x00000, 0x780, BAD_DUMP CRC(f60cdd86) SHA1(e18cc598153b3e108942328ee9c5b9f83b034c41) ) // FIXED BITS (xxxxxx0x)
265
	265
266	266	ROM_REGION( 0x10000, "gfx1", 0 )
267	267	ROM_LOAD( "xyonix1.bin", 0x00000, 0x08000, CRC(3dfa9596) SHA1(52cdbbe18f83cea7248c29588ea3a18c4bb7984f) )
268	268	ROM_LOAD( "xyonix2.bin", 0x08000, 0x08000, CRC(db87343e) SHA1(62bc30cd65b2f8976cd73a0b349a9ccdb3faaad2) )
r248551	r248552
274	274	/* GAME drivers **************************************************************/
275	275
276	276	GAME( 1989, xyonix, 0, xyonix, xyonix, driver_device, 0, ROT0, "Philko", "Xyonix", GAME_SUPPORTS_SAVE )
277
		No newline at end of file
	277

trunk/src/mame/includes/cclimber.h
r248551	r248552
22	22	m_toprollr_bg_videoram(*this, "bg_videoram"),
23	23	m_toprollr_bg_coloram(*this, "bg_coloram"),
24	24	m_decrypted_opcodes(*this, "decrypted_opcodes") { }
25
	25
26	26	required_device<cpu_device> m_maincpu;
27	27	optional_device<cpu_device> m_audiocpu;
28	28	required_device<gfxdecode_device> m_gfxdecode;

trunk/src/mame/includes/deco32.h
r248551	r248552
116	116
117	117	// nslasher
118	118	DECLARE_WRITE32_MEMBER(nslasher_eeprom_w);
119
	119
120	120	// tattass
121	121	DECLARE_WRITE32_MEMBER(tattass_control_w);
122	122
r248551	r248552
205	205	UINT32 m_sprite_ctrl;
206	206	int m_lightgun_port;
207	207	bitmap_rgb32 m_temp_render_bitmap;
208
	208
209	209	DECLARE_READ32_MEMBER(lightgun_r);
210	210	DECLARE_WRITE32_MEMBER(lightgun_w);
211	211	DECLARE_WRITE32_MEMBER(sprite_control_w);

trunk/src/mame/includes/itech8.h
r248551	r248552
40	40	required_device<tms34061_device> m_tms34061;
41	41	required_device<tlc34076_device> m_tlc34076;
42	42	required_device<screen_device> m_screen;
43
	43
44	44	rectangle m_visarea;
45	45
46	46	UINT8 m_grom_bank;
r248551	r248552
165	165	UINT16 sens0, UINT16 sens1, UINT16 sens2, UINT16 sens3);
166	166	void compute_sensors();
167	167	TIMER_CALLBACK_MEMBER( delayed_z80_control_w );
168
	168
169	169	protected:
170	170	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
171	171	};

trunk/src/mame/includes/micro3d.h
r248551	r248552
229	229	virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
230	230	private:
231	231	// internal state
232		// union
233		// {
234		// struct
235		// {
236		// UINT8 m_vcf;
237		// UINT8 m_vcq;
238		// UINT8 m_vca;
239		// UINT8 m_pan;
240		// };
	232	// union
	233	// {
	234	// struct
	235	// {
	236	// UINT8 m_vcf;
	237	// UINT8 m_vcq;
	238	// UINT8 m_vca;
	239	// UINT8 m_pan;
	240	// };
241	241	UINT8 m_dac[4];
242		// };
	242	// };
243	243
244	244	float m_gain;
245	245	UINT32 m_noise_shift;

trunk/src/mame/includes/nbmj9195.h
r248551	r248552
38	38	required_device<dac_device> m_dac2;
39	39	required_device<screen_device> m_screen;
40	40	required_device<palette_device> m_palette;
41
	41
42	42	optional_shared_ptr<UINT8> m_palette_ptr; //shabdama doesn't use it at least for now
43	43
44	44	int m_inputport;

trunk/src/mame/includes/pcktgal.h
r248551	r248552
34	34	DECLARE_WRITE8_MEMBER(adpcm_data_w);
35	35	DECLARE_READ8_MEMBER(adpcm_reset_r);
36	36	DECLARE_WRITE_LINE_MEMBER(adpcm_int);
37
	37
38	38	DECLARE_DRIVER_INIT(pcktgal);
39	39	DECLARE_PALETTE_INIT(pcktgal);
40	40	virtual void machine_start();

trunk/src/mame/includes/taitoair.h
r248551	r248552
75	75	INT16 m_eyecoordBuffer[4]; /* homogeneous */
76	76
77	77	bool m_gradbank;
78
	78
79	79	DECLARE_READ16_MEMBER(dsp_m_r);
80	80	DECLARE_WRITE16_MEMBER(dsp_m_w);
81	81
r248551	r248552
130	130	void fb_copy_op(void);
131	131	void fb_fill_op(void);
132	132	void fb_erase_op(void);
133
	133
134	134	void fill_slope( bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16 header, INT32 x1, INT32 x2, INT32 sl1, INT32 sl2, INT32 y1, INT32 y2, INT32 nx1, INT32 nx2 );
135	135	void fill_poly( bitmap_ind16 &bitmap, const rectangle &cliprect, const struct taitoair_poly *q );
136	136	int projectEyeCoordToScreen(float* projectionMatrix,const int Res,INT16* eyePoint3d,int type);

trunk/src/mame/machine/awboard.c
r248551	r248552
99	99	00000000 - 00800000 FMEM1 flash ROM
100	100	00800000 - 01000000 FMEM2 flash ROM
101	101	01000000 - 02000000 unk, probably mirror of above
102		02000000 - 04000000 MROM1 MROM4 MROM7 MROM10 \
	102	02000000 - 04000000 MROM1 MROM4 MROM7 MROM10 \
103	103	04000000 - 06000000 MROM2 MROM5 MROM8 MROM11 banked mask ROMs
104		06000000 - 08000000 MROM3 MROM6 MROM9 MROM12 /
	104	06000000 - 08000000 MROM3 MROM6 MROM9 MROM12 /
105	105
106	106	Type 3:
107	107
r248551	r248552
116	116
117	117	Development:
118	118
119		00000000 - 00800000 IC12 \
	119	00000000 - 00800000 IC12 \
120	120	..... flash ROMs
121		07800000 - 08000000 IC27 /
	121	07800000 - 08000000 IC27 /
122	122
123
	123
124	124	In short:
125	125
126	126	EPR-ROM

trunk/src/mame/machine/dc.c
r248551	r248552
732	732	#if (defined(__MINGW32__) && (__GNUC__ >= 5))
733	733	#pragma GCC diagnostic pop
734	734	#endif
735

trunk/src/mame/machine/fd1089.c
r248551	r248552
223	223
224	224	fd1089_base_device::fd1089_base_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source)
225	225	: m68000_device(mconfig, tag, owner, clock, shortname, source),
226		m_decrypted_opcodes(*this, ":fd1089_decrypted_opcodes")
	226	m_decrypted_opcodes(*this, ":fd1089_decrypted_opcodes")
227	227	{
228	228	// override the name after the m68000 initializes
229	229	m_name.assign(name);

trunk/src/mame/machine/m1comm.c
r248551	r248552
330	330	#ifdef __M1COMM_SIMULATION__
331	331	void m1comm_device::comm_tick()
332	332	{
333		if (m_linkenable == 0x01)
	333	if (m_linkenable == 0x01)
334	334	{
335	335	int frameStart = 0x0010;
336	336	int frameOffset = 0x0000;
r248551	r248552
568	568	}
569	569	}
570	570	}
571		#endif
		No newline at end of file
	571	#endif

trunk/src/mame/machine/mc8123.h
r248551	r248552
10	10	// an arbitrary amount of banks at 8000-BFFF.
11	11
12	12	void mc8123_decode(UINT8 rom, UINT8 opcodes, const UINT8 *key, int length);
13

trunk/src/mame/machine/pgmcrypt.c
r248551	r248552
1508	1508	int rom_size = 0x200000;
1509	1509
1510	1510	for(i=0; i<rom_size/2; i++) {
1511
1512	1511	UINT16 x = src[i];
1513	1512
1514	1513	// not 100% verified
r248551	r248552
1526	1525	src[i] = x;
1527	1526	}
1528	1527	}
1529

trunk/src/mame/machine/s32comm.c
r248551	r248552
18	18	\| \|---------------------------------\| \|
19	19	\| \|---------------------------------\| LED CN? CN? CNK \|
20	20	\|--------------------------------------------------------------------------------\|
21		Setup:
22		Z80 - Zilog Z0840004PSC Z80 CPU, running at 4.000MHz (DIP40)
23		MB89237A - Fujitsu MB89237A DMA-Controller (DIP20) [most likely i8237A clone]
24		MB89374 - Fujitsu MB89374 Data Link Controller (SDIP42)
25		MB8464 - Fujitsu MB8464 8k x8 SRAM (DIP28)
26		MB8421 - Fujitsu MB8421-12LP 2k x8 SRAM (SDIP52)
	21	Setup:
	22	Z80 - Zilog Z0840004PSC Z80 CPU, running at 4.000MHz (DIP40)
	23	MB89237A - Fujitsu MB89237A DMA-Controller (DIP20) [most likely i8237A clone]
	24	MB89374 - Fujitsu MB89374 Data Link Controller (SDIP42)
	25	MB8464 - Fujitsu MB8464 8k x8 SRAM (DIP28)
	26	MB8421 - Fujitsu MB8421-12LP 2k x8 SRAM (SDIP52)
27	27
28		Board:
29		837-9409 F1 Super Lap
	28	Board:
	29	837-9409 F1 Super Lap
30	30
31		EEPROM:
32		14084.17 Rad Rally
33		15612.17 F1 Super Lap
	31	EEPROM:
	32	14084.17 Rad Rally
	33	15612.17 F1 Super Lap
34	34
35	35	Sega System Multi32 Comm PCB 837-8792-91
36	36	( http://images.arianchen.de/sega-comm/orunners-front.jpg )
r248551	r248552
49	49	\| \|---------------------------------\| \|---------------------------------\| \|
50	50	\| CN8 CN9 \|
51	51	\|--------------------------------------------------------------------------------\|
52		Setup:
53		15033.17 - INTEL D27C100 128k x8 EPROM (DIP32, labelled 'EPR-15033')
54		Z80 - Zilog Z0840004PSC Z80 CPU, running at 4.000MHz (DIP40)
55		MB89237A - Fujitsu MB89237A DMA-Controller (DIP20) [most likely i8237A clone]
56		MB89374 - Fujitsu MB89374 Data Link Controller (SDIP42)
57		MB8421 - Fujitsu MB8421-12LP 2k x8 SRAM (SDIP52)
58		MB8464A - Fujitsu MB8464-10LL 8k x8 SRAM (DIP28)
59		315-5611 - Lattice GAL16V8A PAL (DIP20)
60		315-5506 - Lattice GAL16V8A PAL (DIP20)
	52	Setup:
	53	15033.17 - INTEL D27C100 128k x8 EPROM (DIP32, labelled 'EPR-15033')
	54	Z80 - Zilog Z0840004PSC Z80 CPU, running at 4.000MHz (DIP40)
	55	MB89237A - Fujitsu MB89237A DMA-Controller (DIP20) [most likely i8237A clone]
	56	MB89374 - Fujitsu MB89374 Data Link Controller (SDIP42)
	57	MB8421 - Fujitsu MB8421-12LP 2k x8 SRAM (SDIP52)
	58	MB8464A - Fujitsu MB8464-10LL 8k x8 SRAM (DIP28)
	59	315-5611 - Lattice GAL16V8A PAL (DIP20)
	60	315-5506 - Lattice GAL16V8A PAL (DIP20)
61	61
62		Board:
63		837-8792 OutRunners, Stadium Cross
	62	Board:
	63	837-8792 OutRunners, Stadium Cross
64	64
65		EEPROM:
66		15033.17 OutRunners, Stadium Cross
	65	EEPROM:
	66	15033.17 OutRunners, Stadium Cross
67	67	*/
68	68
69	69	#include "machine/s32comm.h"
r248551	r248552
198	198	m_linkalive = 0x00;
199	199	m_linkcount = 0x00;
200	200	m_linktimer = 0x04; //0x00E8; // 58 fps * 4s
201
	201
202	202	comm_tick();
203	203	}
204	204	#endif
r248551	r248552
213	213	{
214	214	if (!m_cn)
215	215	return;
216
	216
217	217	m_fg = data & 0x01;
218	218	}
219	219
r248551	r248552
229	229	void s32comm_device::set_linktype(UINT16 linktype)
230	230	{
231	231	m_linktype = linktype;
232
	232
233	233	switch (m_linktype)
234	234	{
235	235	case 14084:
r248551	r248552
268	268
269	269	void s32comm_device::comm_tick_14084()
270	270	{
271		if (m_linkenable == 0x01)
	271	if (m_linkenable == 0x01)
272	272	{
273	273	int frameStart = 0x0480;
274	274	int frameOffset = 0x0000;
r248551	r248552
287	287	{
288	288	// waiting...
289	289	m_shared[4] = 0x00;
290
	290
291	291	// check rx socket
292	292	if (!m_line_rx.is_open())
293	293	{
294	294	printf("S32COMM: listen on %s\n", m_localhost);
295	295	m_line_rx.open(m_localhost);
296	296	}
297
	297
298	298	// check tx socket
299	299	if (!m_line_tx.is_open())
300	300	{
301	301	printf("S32COMM: connect to %s\n", m_remotehost);
302	302	m_line_tx.open(m_remotehost);
303	303	}
304
	304
305	305	// if both sockets are there check ring
306	306	if ((m_line_rx.is_open()) && (m_line_tx.is_open()))
307	307	{
r248551	r248552
338	338	m_line_tx.write(m_buffer, dataSize);
339	339	}
340	340	}
341
	341
342	342	// 0xFE - link size
343	343	else if (idx == 0xFE)
344	344	{
r248551	r248552
349	349	// slave and relay forward message
350	350	m_line_tx.write(m_buffer, dataSize);
351	351	}
352
	352
353	353	// consider it done
354	354	printf("S32COMM: link established - id %02x of %02x\n", m_linkid, m_linkcount);
355	355	m_linkalive = 0x01;
356
	356
357	357	// write to shared mem
358	358	m_shared[4] = 0x01;
359	359	m_shared[1] = m_linkid;
r248551	r248552
371	371	}
372	372	printf("S32COMM: droped a message...\n");
373	373	}
374
	374
375	375	if (m_linkalive == 0x00)
376	376	recv = m_line_rx.read(m_buffer, dataSize);
377	377	else
378	378	recv = 0;
379	379	}
380
	380
381	381	// if we are master and link is not yet established
382	382	if (isMaster && (m_linkalive == 0x00))
383	383	{
r248551	r248552
405	405	m_shared[1] = m_linkid;
406	406	m_shared[0] = m_linkcount;
407	407	}
408
	408
409	409	else if (m_linktimer > 0x02)
410	410	{
411	411	// decrease delay timer
r248551	r248552
415	415	}
416	416	}
417	417	}
418		}
	418	}
419	419
420	420	// update "ring buffer" if link established
421	421	if (m_linkalive == 0x01)
r248551	r248552
470	470	}
471	471	recv = m_line_rx.read(m_buffer, dataSize);
472	472	}
473
	473
474	474	// update "ring buffer" if link established
475	475	// live relay does not send data
476	476	if (m_linkid != 0x00 && m_shared[3] != 0x00)
r248551	r248552
486	486	// push message to other nodes
487	487	m_line_tx.write(m_buffer, dataSize);
488	488
489		// master sends some additional status bytes
	489	// master sends some additional status bytes
490	490	if (isMaster){
491	491	m_buffer[0] = 0xF0;
492	492	for (int j = 0x00 ; j < frameSize ; j++)
r248551	r248552
501	501	m_line_tx.write(m_buffer, dataSize);
502	502	}
503	503	}
504
	504
505	505	// clear 03
506	506	m_shared[3] = 0x00;
507	507	}
508		}
	508	}
509	509	}
510	510
511	511	void s32comm_device::comm_tick_15033()
512	512	{
513		if (m_linkenable == 0x01)
	513	if (m_linkenable == 0x01)
514	514	{
515	515	int frameStartTX = 0x0710;
516	516	int frameStartRX = 0x0010;
r248551	r248552
540	540	{
541	541	// waiting...
542	542	m_shared[4] = 0x00;
543
	543
544	544	// check rx socket
545	545	if (!m_line_rx.is_open())
546	546	{
547	547	printf("S32COMM: listen on %s\n", m_localhost);
548	548	m_line_rx.open(m_localhost);
549	549	}
550
	550
551	551	// check tx socket
552	552	if (!m_line_tx.is_open())
553	553	{
554	554	printf("S32COMM: connect to %s\n", m_remotehost);
555	555	m_line_tx.open(m_remotehost);
556	556	}
557
	557
558	558	// if both sockets are there check ring
559	559	if ((m_line_rx.is_open()) && (m_line_tx.is_open()))
560	560	{
r248551	r248552
591	591	m_line_tx.write(m_buffer, dataSize);
592	592	}
593	593	}
594
	594
595	595	// 0xFE - link size
596	596	else if (idx == 0xFE)
597	597	{
r248551	r248552
602	602	// slave and relay forward message
603	603	m_line_tx.write(m_buffer, dataSize);
604	604	}
605
	605
606	606	// consider it done
607	607	printf("S32COMM: link established - id %02x of %02x\n", m_linkid, m_linkcount);
608	608	m_linkalive = 0x01;
609
	609
610	610	// write to shared mem
611	611	m_shared[4] = 0x01;
612	612	m_shared[1] = m_linkid;
r248551	r248552
624	624	}
625	625	printf("S32COMM: droped a message...\n");
626	626	}
627
	627
628	628	if (m_linkalive == 0x00)
629	629	recv = m_line_rx.read(m_buffer, dataSize);
630	630	else
631	631	recv = 0;
632	632	}
633
	633
634	634	// if we are master and link is not yet established
635	635	if (isMaster && (m_linkalive == 0x00))
636	636	{
r248551	r248552
658	658	m_shared[1] = m_linkid;
659	659	m_shared[0] = m_linkcount;
660	660	}
661
	661
662	662	else if (m_linktimer > 0x02)
663	663	{
664	664	// decrease delay timer
r248551	r248552
668	668	}
669	669	}
670	670	}
671		}
	671	}
672	672
673	673	// update "ring buffer" if link established
674	674	if (m_linkalive == 0x01)
r248551	r248552
723	723	}
724	724	recv = m_line_rx.read(m_buffer, dataSize);
725	725	}
726
	726
727	727	// update "ring buffer" if link established
728	728	// live relay does not send data
729	729	if (m_linkid != 0x00 && m_shared[3] != 0x00)
r248551	r248552
739	739	// push message to other nodes
740	740	m_line_tx.write(m_buffer, dataSize);
741	741
742		// master sends some additional status bytes
	742	// master sends some additional status bytes
743	743	if (isMaster){
744	744	m_buffer[0] = 0xF0;
745	745	for (int j = 0x00 ; j < frameSize ; j++)
r248551	r248552
757	757	// clear 03
758	758	m_shared[3] = 0x00;
759	759	}
760		}
	760	}
761	761	}
762	762
763	763	void s32comm_device::comm_tick_15612()
764	764	{
765		if (m_linkenable == 0x01)
	765	if (m_linkenable == 0x01)
766	766	{
767	767	int frameStart = 0x0010;
768	768	int frameOffset = 0x0000;
r248551	r248552
781	781	{
782	782	// waiting...
783	783	m_shared[0] = 0x05;
784
	784
785	785	// check rx socket
786	786	if (!m_line_rx.is_open())
787	787	{
788	788	printf("S32COMM: listen on %s\n", m_localhost);
789	789	m_line_rx.open(m_localhost);
790	790	}
791
	791
792	792	// check tx socket
793	793	if (!m_line_tx.is_open())
794	794	{
795	795	printf("S32COMM: connect to %s\n", m_remotehost);
796	796	m_line_tx.open(m_remotehost);
797	797	}
798
	798
799	799	// if both sockets are there check ring
800	800	if ((m_line_rx.is_open()) && (m_line_tx.is_open()))
801	801	{
r248551	r248552
832	832	m_line_tx.write(m_buffer, dataSize);
833	833	}
834	834	}
835
	835
836	836	// 0xFE - link size
837	837	else if (idx == 0xFE)
838	838	{
r248551	r248552
843	843	// slave and relay forward message
844	844	m_line_tx.write(m_buffer, dataSize);
845	845	}
846
	846
847	847	// consider it done
848	848	printf("S32COMM: link established - id %02x of %02x\n", m_linkid, m_linkcount);
849	849	m_linkalive = 0x01;
850
	850
851	851	// write to shared mem
852	852	m_shared[0] = 0x01;
853	853	m_shared[2] = m_linkid;
r248551	r248552
865	865	}
866	866	printf("S32COMM: droped a message...\n");
867	867	}
868
	868
869	869	if (m_linkalive == 0x00)
870	870	recv = m_line_rx.read(m_buffer, dataSize);
871	871	else
872	872	recv = 0;
873	873	}
874
	874
875	875	// if we are master and link is not yet established
876	876	if (isMaster && (m_linkalive == 0x00))
877	877	{
r248551	r248552
899	899	m_shared[2] = m_linkid;
900	900	m_shared[3] = m_linkcount;
901	901	}
902
	902
903	903	else if (m_linktimer > 0x02)
904	904	{
905	905	// decrease delay timer
r248551	r248552
909	909	}
910	910	}
911	911	}
912		}
	912	}
913	913
914	914	// update "ring buffer" if link established
915	915	if (m_linkalive == 0x01)
r248551	r248552
964	964	}
965	965	recv = m_line_rx.read(m_buffer, dataSize);
966	966	}
967
	967
968	968	// update "ring buffer" if link established
969	969	// live relay does not send data
970	970	if (m_linkid != 0x00 && m_shared[4] != 0x00)
r248551	r248552
980	980	// push message to other nodes
981	981	m_line_tx.write(m_buffer, dataSize);
982	982
983		// master sends some additional status bytes
	983	// master sends some additional status bytes
984	984	if (isMaster){
985	985	m_buffer[0] = 0xF0;
986	986	for (int j = 0x00 ; j < frameSize ; j++)

trunk/src/mame/machine/s32comm.h
r248551	r248552
11	11
12	12	#define MCFG_S32COMM_ADD(_tag ) \
13	13	MCFG_DEVICE_ADD(_tag, S32COMM, 0)
14
	14
15	15	//**************************************************************************
16	16	// TYPE DEFINITIONS
17	17	//**************************************************************************
r248551	r248552
45	45	DECLARE_READ8_MEMBER(fg_r);
46	46	DECLARE_WRITE8_MEMBER(fg_w);
47	47
48		// IRQ logic - 5 = VINT, 7 = DLC
	48	// IRQ logic - 5 = VINT, 7 = DLC
49	49	void check_vint_irq();
50	50	#ifdef __S32COMM_SIMULATION__
51	51	void set_linktype(UINT16 linktype);
r248551	r248552
58	58
59	59	private:
60	60	UINT8 m_shared[0x800]; // 2k shared memory
61		UINT8 m_zfg; // z80 flip gate? purpose unknown, bit0 is stored
62		UINT8 m_cn; // bit0 is used to enable/disable the comm board
63		UINT8 m_fg; // flip gate? purpose unknown, bit0 is stored, bit7 is connected to ZFG bit 0
64
	61	UINT8 m_zfg; // z80 flip gate? purpose unknown, bit0 is stored
	62	UINT8 m_cn; // bit0 is used to enable/disable the comm board
	63	UINT8 m_fg; // flip gate? purpose unknown, bit0 is stored, bit7 is connected to ZFG bit 0
	64
65	65	emu_file m_line_rx; // rx line - can be either differential, simple serial or toslink
66	66	emu_file m_line_tx; // tx line - is differential, simple serial and toslink
67	67	char m_localhost[256];
68	68	char m_remotehost[256];
69	69	UINT8 m_buffer[0x800];
70
	70
71	71	#ifdef __S32COMM_SIMULATION__
72	72	UINT8 m_linkenable;
73	73	UINT16 m_linktimer;
r248551	r248552
76	76	UINT8 m_linkcount;
77	77
78	78	UINT16 m_linktype;
79
	79
80	80	void comm_tick();
81
	81
82	82	void comm_tick_14084();
83	83	void comm_tick_15033();
84	84	void comm_tick_15612();

trunk/src/mame/machine/segacrp2.c
r248551	r248552
48	48
49	49
50	50	void sega_decode_2(UINT8 rom, UINT8 decrypted,
51		const UINT8 xor_table[128],const int swap_table[128])
	51	const UINT8 xor_table[128],const int swap_table[128])
52	52	{
53	53	static const UINT8 swaptable[24][4] =
54	54	{

trunk/src/mame/machine/segacrp2.h
r248551	r248552
2	2	// copyright-holders:Nicola Salmoria
3	3
4	4	void sega_decode_2(UINT8 rom, UINT8 decrypted,
5		const UINT8 xor_table[128],const int swap_table[128]);
	5	const UINT8 xor_table[128],const int swap_table[128]);
6	6
7	7	void sega_decode_317(UINT8 rom, UINT8 decrypted, int shift);

trunk/src/mame/mess.lst
r248551	r248552
1580	1580	fsa1st
1581	1581
1582	1582	// Microsoft
1583		xbox
	1583	xbox
1584	1584
1585	1585	// NASCOM Microcomputers
1586	1586	nascom1 // 1978 Nascom 1

trunk/src/mame/video/deco32.c
r248551	r248552
159	159	VIDEO_START_MEMBER(deco32_state,captaven)
160	160	{
161	161	m_has_ace_ram=0;
162
	162
163	163	deco32_state::video_start();
164	164	}
165	165
r248551	r248552
168	168	m_dirty_palette = auto_alloc_array(machine(), UINT8, 4096);
169	169	m_sprgen->alloc_sprite_bitmap();
170	170	m_has_ace_ram=0;
171
	171
172	172	save_pointer(NAME(m_dirty_palette), 4096);
173	173	deco32_state::video_start();
174	174	}
r248551	r248552
184	184	m_sprgen2->alloc_sprite_bitmap();
185	185	memset(m_dirty_palette,0,4096);
186	186	m_has_ace_ram=1;
187
	187
188	188	save_pointer(NAME(m_dirty_palette), 4096);
189	189	save_item(NAME(m_ace_ram_dirty));
190	190	save_item(NAME(m_spriteram16_2));
191	191	save_item(NAME(m_spriteram16_2_buffered));
192
	192
193	193	deco32_state::video_start();
194	194	}
195	195
r248551	r248552
207	207	m_screen->register_screen_bitmap(m_temp_render_bitmap);
208	208
209	209	memset(m_dirty_palette,0,4096);
210
	210
211	211	m_has_ace_ram=0;
212	212
213	213	save_item(NAME(m_sprite_ctrl));

trunk/src/mame/video/hexion.c
r248551	r248552
51	51	m_vram[0] = memregion("maincpu")->base() + 0x30000;
52	52	m_vram[1] = m_vram[0] + 0x2000;
53	53	m_unkram = m_vram[1] + 0x2000;
54
	54
55	55	membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x2000);
56	56	}
57	57

trunk/src/mame/video/itech8.c
r248551	r248552
149	149	/* fetch the GROM base */
150	150	m_grom_base = memregion("grom")->base();
151	151	m_grom_size = memregion("grom")->bytes();
152
	152
153	153	save_item(NAME(m_blitter_data));
154	154	save_item(NAME(m_blit_in_progress));
155	155	save_item(NAME(m_page_select));

trunk/src/mame/video/namcona1.c
r248551	r248552
185	185	m_shaperam.resize(0x8000);
186	186
187	187	m_gfxdecode->gfx(2)->set_source(&m_shaperam[0]);
188
	188
189	189	save_item(NAME(m_shaperam));
190	190	save_item(NAME(m_palette_is_dirty));
191
	191
192	192	machine().save().register_postload(save_prepost_delegate(FUNC(namcona1_state::postload), this));
193	193	} /* video_start */
194	194

trunk/src/mame/video/naughtyb.c
r248551	r248552
107	107
108	108	/* Naughty Boy has a virtual screen twice as large as the visible screen */
109	109	m_tmpbitmap.allocate(688,288,m_screen->format());
110
	110
111	111	save_item(NAME(m_cocktail));
112	112	save_item(NAME(m_palreg));
113	113	save_item(NAME(m_bankreg));

trunk/src/mame/video/nbmj9195.c
r248551	r248552
372	372	{
373	373	int width = m_screen->width();
374	374	int height = m_screen->height();
375
	375
376	376	m_blitter_timer = timer_alloc(TIMER_BLITTER);
377	377
378	378	m_screen->register_screen_bitmap(m_tmpbitmap[0]);
r248551	r248552
381	381	m_scanline[0] = m_scanline[1] = SCANLINE_MIN;
382	382	m_nb19010_busyflag = 1;
383	383	m_gfxdraw_mode = 0;
384
	384
385	385	save_item(NAME(m_scrollx));
386	386	save_item(NAME(m_scrolly));
387	387	save_item(NAME(m_scrollx_raster));
r248551	r248552
424	424	m_nb19010_busyflag = 1;
425	425	m_gfxdraw_mode = 1;
426	426	m_screen_refresh = 1;
427
	427
428	428	save_item(NAME(m_scrollx));
429	429	save_item(NAME(m_scrolly));
430	430	save_item(NAME(m_scrollx_raster));

trunk/src/mame/video/segas32.c
r248551	r248552
1103	1103	if (!flipx)
1104	1104	{
1105	1105	srcx = cliprect.min_x + xscroll;
1106		srcxstep = 1;
	1106	srcxstep = 1;
1107	1107	}
1108	1108	else
1109		{
	1109	{
1110	1110	srcx = cliprect.max_x + xscroll;
1111	1111	srcxstep = -1;
1112	1112	}

trunk/src/mame/video/shadfrce.c
r248551	r248552
103	103
104	104	void shadfrce_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int y_offset )
105	105	{
106
107
108	106	/* \| ---- ---- hhhf Fe-Y \| ---- ---- yyyy yyyy \| ---- ---- TTTT TTTT \| ---- ---- tttt tttt \|
109	107	\| ---- ---- -pCc cccX \| ---- ---- xxxx xxxx \| ---- ---- ---- ---- \| ---- ---- ---- ---- \| */
110	108
r248551	r248552
125	123	int hcount;
126	124	while (source >= finish)
127	125	{
128
129	126	int enable = ((source[0] & 0x0004));
130	127
131	128	if (enable)

trunk/src/mame/video/starcrus.c
r248551	r248552
26	26
27	27	m_proj1_vid = auto_bitmap_ind16_alloc(machine(), 16, 16);
28	28	m_proj2_vid = auto_bitmap_ind16_alloc(machine(), 16, 16);
29
	29
30	30	save_item(NAME(m_s1_x));
31	31	save_item(NAME(m_s1_y));
32	32	save_item(NAME(m_s2_x));

trunk/src/mame/video/taitoair.c
r248551	r248552
96	96	for (offs = start_offset; offs >= 0; offs -= 0x008 / 2)
97	97	{
98	98	/*!
99		Starting at a particular sequence, sprite DMA seems to stop there and resume via "something",
	99	Starting at a particular sequence, sprite DMA seems to stop there and resume via "something",
100	100	effectively drawing any other sprite with better priority in the framebuffer scheme of things.
101
102		@todo reported sequence for DMA pause flag is 0x0c** 0x0000 0x0000 0x0000.
103		Verify how exactly via HW test. Continuing may be determined by a DMA bit write.
	101
	102	@todo reported sequence for DMA pause flag is 0x0c** 0x0000 0x0000 0x0000.
	103	Verify how exactly via HW test. Continuing may be determined by a DMA bit write.
104	104	*/
105	105	if(m_tc0080vco->sprram_r(space, offs + 0, 0xffff) == 0xc00 \|\|
106		m_tc0080vco->sprram_r(space, offs + 0, 0xffff) == 0xcff) // Air Inferno
	106	m_tc0080vco->sprram_r(space, offs + 0, 0xffff) == 0xcff) // Air Inferno
107	107	return offs - 8/2;
108
	108
109	109	x0 = m_tc0080vco->sprram_r(space, offs + 1, 0xffff) & 0x3ff;
110	110	y0 = m_tc0080vco->sprram_r(space, offs + 0, 0xffff) & 0x3ff;
111	111	zoomx = (m_tc0080vco->sprram_r(space, offs + 2, 0xffff) & 0x7f00) >> 8;
r248551	r248552
113	113	tile_offs = (m_tc0080vco->sprram_r(space, offs + 3, 0xffff) & 0x1fff) << 2;
114	114	ysize = size[(m_tc0080vco->sprram_r(space, offs, 0xffff) & 0x0c00) >> 10];
115	115
116
	116
117	117	if (tile_offs)
118	118	{
119	119	/* Convert zoomy value to real value as zoomx */
r248551	r248552
198	198	}
199	199	}
200	200	}
201
	201
202	202	return 0;
203	203	}
204	204
r248551	r248552
401	401	cliprect.min_y = 3*16;
402	402	cliprect.max_x = m_screen->width() - 1;
403	403	cliprect.max_y = m_screen->height() - 1;
404
	404
405	405	/* clear screen fb */
406	406	m_framebuffer[1]->fill(0, cliprect);
407	407	/* copy buffer fb into screen fb (at this stage we are ready to draw) */
r248551	r248552
421	421	cliprect.min_y = 3*16;
422	422	cliprect.max_x = m_screen->width() - 1;
423	423	cliprect.max_y = m_screen->height() - 1;
424
	424
425	425	m_framebuffer[0]->fill(0, cliprect);
426	426	//m_framebuffer[1]->fill(0, cliprect);
427	427	}
r248551	r248552
437	437	cliprect.min_y = 3*16;
438	438	cliprect.max_x = m_screen->width() - 1;
439	439	cliprect.max_y = m_screen->height() - 1;
440
	440
441	441	if (m_line_ram[0x3fff])
442	442	{
443	443	int adr = 0x3fff;
r248551	r248552
542	542	}
543	543	if(m_gradbank == true)
544	544	base\|= 0x1000;
545
	545
546	546	*dest++ = base \| (cntr >= 0x83f000 ? 0x3f : (cntr >> 12) & 0x3f);
547
	547
548	548	c1b += inc1x;
549	549	c2b += inc2x;
550	550	}
551	551	counter1 += inc1y;
552	552	counter2 += inc2y;
553	553	}
554
555	554
556	555
	556
557	557	copybitmap_trans(bitmap, *m_framebuffer[1], 0, 0, 0, 0, cliprect, 0);
558	558
559	559	m_tc0080vco->tilemap_draw(screen, bitmap, cliprect, 0, 0, 0);
560	560
561	561	sprite_ptr = draw_sprites(bitmap, cliprect);
562	562
563		m_tc0080vco->tilemap_draw(screen, bitmap, cliprect, 1, 0, 0);
564
	563	m_tc0080vco->tilemap_draw(screen, bitmap, cliprect, 1, 0, 0);
	564
565	565	m_tc0080vco->tilemap_draw(screen, bitmap, cliprect, 2, 0, 0);
566	566
567	567	draw_sprites(bitmap, cliprect, sprite_ptr);

trunk/src/mame/video/tank8.c
r248551	r248552
111	111	/* VBLANK starts on scanline #256 and ends on scanline #24 */
112	112
113	113	m_tilemap->set_scrolly(0, 2 * 24);
114
	114
115	115	save_item(NAME(m_collision_index));
116	116	}
117	117

trunk/src/mame/video/vsystem_spr.c
r248551	r248552
85	85	m_pal_mask = 0x3f;
86	86
87	87	m_newtilecb = vsystem_tile_indirection_delegate(FUNC(vsystem_spr_device::tile_callback_noindirect), this);
88
	88
89	89	memset(&m_curr_sprite, 0, sizeof(m_curr_sprite));
90	90	}
91	91
r248551	r248552
177	177	{
178	178	// bind our handler
179	179	m_newtilecb.bind_relative_to(*owner());
180
	180
181	181	save_item(NAME(m_pal_base));
182
	182
183	183	save_item(NAME(m_curr_sprite.ox));
184	184	save_item(NAME(m_curr_sprite.xsize));
185	185	save_item(NAME(m_curr_sprite.zoomx));

trunk/src/mess/drivers/apple2.c
r248551	r248552
1569	1569	COMP( 1982, maxxi, apple2, 0, apple2p, apple2p, driver_device, 0, "Polymax", "Maxxi", GAME_SUPPORTS_SAVE )
1570	1570	COMP( 1982, prav82, apple2, 0, apple2p, apple2p, driver_device, 0, "Pravetz", "Pravetz 82", GAME_SUPPORTS_SAVE )
1571	1571	COMP( 1982, ace100, apple2, 0, apple2, apple2p, driver_device, 0, "Franklin Computer", "Franklin Ace 100", GAME_SUPPORTS_SAVE )
1572		COMP( 1982, uniap2en, apple2, 0, apple2p, apple2p, driver_device, 0, "Unitron Eletrônica", "Unitron AP II (in English)", GAME_SUPPORTS_SAVE )
1573		COMP( 1982, uniap2pt, apple2, 0, apple2p, apple2p, driver_device, 0, "Unitron Eletrônica", "Unitron AP II (in Brazilian Portuguese)", GAME_SUPPORTS_SAVE )
	1572	COMP( 1982, uniap2en, apple2, 0, apple2p, apple2p, driver_device, 0, "Unitron Eletr??nica", "Unitron AP II (in English)", GAME_SUPPORTS_SAVE )
	1573	COMP( 1982, uniap2pt, apple2, 0, apple2p, apple2p, driver_device, 0, "Unitron Eletr??nica", "Unitron AP II (in Brazilian Portuguese)", GAME_SUPPORTS_SAVE )
1574	1574	COMP( 1983, agat7, apple2, 0, apple2p, apple2p, driver_device, 0, "Agat", "Agat-7", GAME_NOT_WORKING) // disk controller ROM JSRs to $FCA8 which is a delay on apple II, illegal instruction crash here :(
1575	1575	// reverse font direction -\/
1576	1576	COMP( 1984, ivelultr, apple2, 0, apple2p, apple2p, driver_device, 0, "Ivasim", "Ivel Ultra", GAME_SUPPORTS_SAVE )

trunk/src/mess/drivers/casloopy.c
r248551	r248552
420	420	AM_RANGE(0x04051000, 0x040511ff) AM_READWRITE16(pal_r, pal_w, 0xffffffff)
421	421	AM_RANGE(0x04058000, 0x04058007) AM_READWRITE16(vregs_r, vregs_w, 0xffffffff)
422	422	AM_RANGE(0x0405b000, 0x0405b00f) AM_RAM AM_SHARE("vregs") // RGB555 brightness control plus scrolling
423		// AM_RANGE(0x05ffff00, 0x05ffffff) AM_READWRITE16(sh7021_r, sh7021_w, 0xffffffff)
	423	// AM_RANGE(0x05ffff00, 0x05ffffff) AM_READWRITE16(sh7021_r, sh7021_w, 0xffffffff)
424	424	// AM_RANGE(0x05ffff00, 0x05ffffff) - SH7021 internal i/o
425	425	AM_RANGE(0x06000000, 0x061fffff) AM_READ(cart_r)
426	426	AM_RANGE(0x07000000, 0x070003ff) AM_RAM AM_SHARE("oram")// on-chip RAM, actually at 0xf000000 (1 kb)

trunk/src/mess/drivers/coleco.c
r248551	r248552
354	354	Unreleased Brazilian Colecovision clone by Microdigital.
355	355
356	356	It was never released and the only known prototypes were uncovered by an ex-employee of Microdigital
357		called Cláudio Cassens who donated it to collectors (Eduardo Luccas) in June 2015.
	357	called Cl??udio Cassens who donated it to collectors (Eduardo Luccas) in June 2015.
358	358	-- Felipe Sanches
359	359	*/
360	360	ROM_START (onyx)

trunk/src/mess/drivers/daruma.c
r248551	r248552
23	23	class daruma_state : public driver_device
24	24	{
25	25	public:
26		daruma_state(const machine_config &mconfig, device_type type, const char *tag)
27		: driver_device(mconfig, type, tag),
28		m_maincpu(*this, "maincpu"),
	26	daruma_state(const machine_config &mconfig, device_type type, const char *tag)
	27	: driver_device(mconfig, type, tag),
	28	m_maincpu(*this, "maincpu"),
29	29	m_speaker(*this, "speaker") { }
30	30
31		DECLARE_WRITE8_MEMBER(port_w);
32		DECLARE_READ8_MEMBER(port_r);
	31	DECLARE_WRITE8_MEMBER(port_w);
	32	DECLARE_READ8_MEMBER(port_r);
33	33
34	34	DECLARE_READ8_MEMBER(dev0_r);
35	35	DECLARE_WRITE8_MEMBER(dev1_w);
36	36	DECLARE_WRITE8_MEMBER(dev2_w);
37	37	DECLARE_READ8_MEMBER(dev4_r);
38		required_device<cpu_device> m_maincpu;
	38	required_device<cpu_device> m_maincpu;
39	39	required_device<speaker_sound_device> m_speaker;
40		char port0, port1, port2, port3;
	40	char port0, port1, port2, port3;
41	41	};
42	42
43	43	WRITE8_MEMBER(daruma_state::port_w)
44	44	{
45	45	// printf("port_w: write %02X to PORT (offset=%02X)\n", data, offset);
46		switch(offset)
47		{
48		case MCS51_PORT_P0: port0=data;
49		case MCS51_PORT_P1: port1=data;
50		case MCS51_PORT_P2: port2=data;
51		case MCS51_PORT_P3: port3=data;
52		}
	46	switch(offset)
	47	{
	48	case MCS51_PORT_P0: port0=data;
	49	case MCS51_PORT_P1: port1=data;
	50	case MCS51_PORT_P2: port2=data;
	51	case MCS51_PORT_P3: port3=data;
	52	}
53	53	}
54	54
55	55	READ8_MEMBER(daruma_state::port_r)
56	56	{
57		switch(offset)
58		{
59		case MCS51_PORT_P0: printf("port_r: read %02X from PORT0\n", port0); return port0;
60		case MCS51_PORT_P1: printf("port_r: read %02X from PORT1\n", port1); return port1;
61		case MCS51_PORT_P2: printf("port_r: read %02X from PORT2\n", port2); return port2;
62		case MCS51_PORT_P3: printf("port_r: read %02X from PORT3\n", port3); return port3;
63		}
64		return 0;
	57	switch(offset)
	58	{
	59	case MCS51_PORT_P0: printf("port_r: read %02X from PORT0\n", port0); return port0;
	60	case MCS51_PORT_P1: printf("port_r: read %02X from PORT1\n", port1); return port1;
	61	case MCS51_PORT_P2: printf("port_r: read %02X from PORT2\n", port2); return port2;
	62	case MCS51_PORT_P3: printf("port_r: read %02X from PORT3\n", port3); return port3;
	63	}
	64	return 0;
65	65	}
66	66
67	67	READ8_MEMBER(daruma_state::dev0_r)
68	68	{
69		return 0xFF;
	69	return 0xFF;
70	70	}
71	71
72	72	READ8_MEMBER(daruma_state::dev4_r)
73	73	{
74		return ioport("switches")->read();
	74	return ioport("switches")->read();
75	75	}
76	76
77	77	WRITE8_MEMBER(daruma_state::dev1_w)
78	78	{
79		//while attempting to identify which bit is used for
80		//controlling the buzzer, here's what I heard from each of
81		//the signals on this address:
	79	//while attempting to identify which bit is used for
	80	//controlling the buzzer, here's what I heard from each of
	81	//the signals on this address:
82	82
83		//0x80 serial comm.? (noise)
84		//0x20 LED? (3 clicks)
85		//0x10 LED? (1 click)
86		//0x08 serial comm.? click & noise
87		//0x04 LED? (2 clicks)
88		//0x02 motor control or printer heads? (I hear a series of rhythmic pulses)
89		//0x01 LED? (2 clicks)
	83	//0x80 serial comm.? (noise)
	84	//0x20 LED? (3 clicks)
	85	//0x10 LED? (1 click)
	86	//0x08 serial comm.? click & noise
	87	//0x04 LED? (2 clicks)
	88	//0x02 motor control or printer heads? (I hear a series of rhythmic pulses)
	89	//0x01 LED? (2 clicks)
90	90	m_speaker->level_w(data & 0x02);
91	91	}
92	92
93	93	WRITE8_MEMBER(daruma_state::dev2_w)
94	94	{
95		//while attempting to identify which bit is used for
96		//controlling the buzzer, here's what I heard from each of
97		//the signals on this address:
	95	//while attempting to identify which bit is used for
	96	//controlling the buzzer, here's what I heard from each of
	97	//the signals on this address:
98	98
99		//0x80: LED? (3 clicks)
100		//0x40: unused?
101		//0x20: unused?
102		//0x10: low freq brief beep followed by a click
103		//0x08: low freq brief noise followed by a click
104		//0x04: low freq brief beep followed by a click
105		//0x02: low freq brief beep followed by a click
106		//0x01: low freq brief noise
	99	//0x80: LED? (3 clicks)
	100	//0x40: unused?
	101	//0x20: unused?
	102	//0x10: low freq brief beep followed by a click
	103	//0x08: low freq brief noise followed by a click
	104	//0x04: low freq brief beep followed by a click
	105	//0x02: low freq brief beep followed by a click
	106	//0x01: low freq brief noise
107	107	//m_speaker->level_w(data & 0x01);
108	108	}
109	109
110	110	static ADDRESS_MAP_START( mem_prg, AS_PROGRAM, 8, daruma_state )
111		AM_RANGE(0x0000, 0xffff) AM_ROM
	111	AM_RANGE(0x0000, 0xffff) AM_ROM
112	112	ADDRESS_MAP_END
113	113
114	114	static ADDRESS_MAP_START( mem_io, AS_IO, 8, daruma_state )
115		AM_RANGE(0x0000, 0x0000) AM_READ(dev0_r)
116		AM_RANGE(0x1000, 0x1000) AM_WRITE(dev1_w)
	115	AM_RANGE(0x0000, 0x0000) AM_READ(dev0_r)
	116	AM_RANGE(0x1000, 0x1000) AM_WRITE(dev1_w)
117	117	// AM_RANGE(0x2000, 0x2000) AM_WRITE(dev2_w)
118	118	// AM_RANGE(0x3000, 0x3000) AM_WRITE(dev3_w)
119		AM_RANGE(0x4000, 0x4000) AM_READ(dev4_r)
120		AM_RANGE(0x8000, 0xffff) AM_RAM /* 32K CMOS SRAM (HYUNDAY hy62256a) */
121		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(port_r, port_w)
	119	AM_RANGE(0x4000, 0x4000) AM_READ(dev4_r)
	120	AM_RANGE(0x8000, 0xffff) AM_RAM /* 32K CMOS SRAM (HYUNDAY hy62256a) */
	121	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(port_r, port_w)
122	122	ADDRESS_MAP_END
123	123
124	124	//TODO: These buttons and switches are all guesses. We'll need to further investigate this.
125	125	static INPUT_PORTS_START( daruma )
126		PORT_START("buttons")
127		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Paper A") PORT_CODE(KEYCODE_A)
128		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Paper B") PORT_CODE(KEYCODE_B)
	126	PORT_START("buttons")
	127	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Paper A") PORT_CODE(KEYCODE_A)
	128	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Paper B") PORT_CODE(KEYCODE_B)
129	129
130		PORT_START("switches")
131		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN)
132		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN)
133		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN)
134		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN)
135		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN)
136		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN)
137		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN)
138		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Limit Switch") PORT_CODE(KEYCODE_S)
	130	PORT_START("switches")
	131	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	132	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	133	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	134	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	135	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	136	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	137	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN)
	138	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Limit Switch") PORT_CODE(KEYCODE_S)
139	139
140	140	INPUT_PORTS_END
141	141
142	142	static MACHINE_CONFIG_START( daruma, daruma_state )
143		/* basic machine hardware */
144		MCFG_CPU_ADD("maincpu", I80C32,11059200) //verified on pcb
145		MCFG_CPU_PROGRAM_MAP(mem_prg)
146		MCFG_CPU_IO_MAP(mem_io)
	143	/* basic machine hardware */
	144	MCFG_CPU_ADD("maincpu", I80C32,11059200) //verified on pcb
	145	MCFG_CPU_PROGRAM_MAP(mem_prg)
	146	MCFG_CPU_IO_MAP(mem_io)
147	147
148	148	/* sound hardware */
149	149	MCFG_SPEAKER_STANDARD_MONO("mono")
r248551	r248552
161	161	MACHINE_CONFIG_END
162	162
163	163	ROM_START( ds348 )
164		ROM_REGION( 0x10000, "maincpu", 0 )
165		ROM_LOAD( "daruma_ds348_v1_1.rom", 0x0000, 0x10000, CRC(10bf9036) SHA1(d654a13bc582f5384e759ec6fe5309a642bd8e18) )
	164	ROM_REGION( 0x10000, "maincpu", 0 )
	165	ROM_LOAD( "daruma_ds348_v1_1.rom", 0x0000, 0x10000, CRC(10bf9036) SHA1(d654a13bc582f5384e759ec6fe5309a642bd8e18) )
166	166	ROM_END
167	167
168	168	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */

trunk/src/mess/drivers/force68k.c
r248551	r248552
1	1	// license:BSD-3-Clause
2		// copyright-holders:Joakim Larsson Edström
	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/***************************************************************************
4	4
5	5	Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
r248551	r248552
7	7	13/06/2015
8	8
9	9	The info found on the links below is for a later revisions of the board I have
10		but I hope it is somewhat compatible so I can get it up and running at least.
	10	but I hope it is somewhat compatible so I can get it up and running at least.
11	11	My CPU-1 board has proms from 1983 and no rev markings so probably the original.
12	12
13	13	http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
r248551	r248552
27	27	0C0 041 - 0C0 043 ACIA (P3) Host
28	28	0C0 080 - 0C0 082 ACIA (P4) Terminal
29	29	0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
30		0C0 401 - 0C0 42F RTC
	30	0C0 401 - 0C0 42F RTC
31	31	OEO 001 - 0E0 035 PI/T (eg centronics printer)
32	32	OEO 200 - 0E0 2FF FPU
33	33	OEO 300 - 0E0 300 Reset Off
r248551	r248552
59	59
60	60	10. The VMEbus
61	61	---------------
62		The implemented VMEbus Interface includes 24 address, 16 data,
	62	The implemented VMEbus Interface includes 24 address, 16 data,
63	63	6 address modifier and the asynchronous control signals.
64		A single level bus arbiter is provided to build multi master
65		systems. In addition to the bus arbiter, a separate slave bus
	64	A single level bus arbiter is provided to build multi master
	65	systems. In addition to the bus arbiter, a separate slave bus
66	66	arbitration allows selection of the arbitration level (0-3).
67	67
68		The address modifier range .,Short 110 Access« can be selected
69		via a jumper for variable system generation. The 7 interrupt
70		request levels of the VMEbus are fully supported from the
71		SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
	68	The address modifier range .,Short 110 Access?? can be selected
	69	via a jumper for variable system generation. The 7 interrupt
	70	request levels of the VMEbus are fully supported from the
	71	SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
72	72	enabled/disabled via a jumper field.
73	73
74		Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
	74	Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
75	75	SYSFAIL and SYSCLK signal (16 MHz).
76	76
77	77
78	78	TODO:
79		- Finish 2 x ACIA6850, host and remote interface left, terminal works
	79	- Finish 2 x ACIA6850, host and remote interface left, terminal works
80	80	- Finish 1 x 68230 Motorola, Parallel Interface / Timer
81	81	- Connect Port B to a Centronics printer interface
82	82	- Add 1 x Abort Switch
83		- Add configurable serial connector between ACIA:s and
	83	- Add configurable serial connector between ACIA:s and
84	84	- Real terminal emulator, ie rs232 "socket"
85	85	- Debug console
86	86	- Add VME bus driver
r248551	r248552
97	97
98	98	#define BAUDGEN_CLOCK XTAL_1_8432MHz
99	99	/*
100		The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
101		Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
102		that I could find on the CPU-1 board. Here how I calculated the clock for
	100	The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
	101	Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
	102	that I could find on the CPU-1 board. Here how I calculated the clock for
103	103	the factory settings. No need to add selectors until terminal.c supports
104	104	configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
105	105
r248551	r248552
107	107
108	108	3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
109	109
110		Default Jumper Settings of B7:
	110	Default Jumper Settings of B7:
111	111	--------------------------------
112	112	GND 10 - 11 RSA input on 14411
113	113	F1 on 14411 1 - 20 Baud selector of the terminal port
r248551	r248552
117	117	The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
118	118	generates 153600 on the F1 output pin which by default strapping is connected to all
119	119	three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
120
	120
121	121	The selectable outputs from 14411, F1-F16:
122	122	X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
123	123	X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
r248551	r248552
133	133	public:
134	134	force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
135	135	driver_device(mconfig, type, tag),
136		// m_rtc(*this, "rtc")
137		m_maincpu(*this, "maincpu"),
138		m_rtc(*this, "rtc"),
139		m_pit(*this, "pit"),
140		m_aciahost(*this, "aciahost"),
141		m_aciaterm(*this, "aciaterm"),
142		m_aciaremt(*this, "aciaremt")
	136	// m_rtc(*this, "rtc")
	137	m_maincpu(*this, "maincpu"),
	138	m_rtc(*this, "rtc"),
	139	m_pit(*this, "pit"),
	140	m_aciahost(*this, "aciahost"),
	141	m_aciaterm(*this, "aciaterm"),
	142	m_aciaremt(*this, "aciaremt")
143	143	{
144	144	}
145	145
r248551	r248552
162	162	};
163	163
164	164	static ADDRESS_MAP_START(force68k_mem, AS_PROGRAM, 16, force68k_state)
165		ADDRESS_MAP_UNMAP_HIGH
166		AM_RANGE(0x000000, 0x000007) AM_ROM AM_READ(bootvect_r) /* Vectors mapped from System EPROM */
167		AM_RANGE(0x000008, 0x01ffff) AM_RAM /* DRAM */
168		AM_RANGE(0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
169		// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
	165	ADDRESS_MAP_UNMAP_HIGH
	166	AM_RANGE(0x000000, 0x000007) AM_ROM AM_READ(bootvect_r) /* Vectors mapped from System EPROM */
	167	AM_RANGE(0x000008, 0x01ffff) AM_RAM /* DRAM */
	168	AM_RANGE(0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
	169	// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
170	170	AM_RANGE(0x0c0040, 0x0c0041) AM_DEVREADWRITE8("aciahost", acia6850_device, status_r, control_w, 0x00ff)
171	171	AM_RANGE(0x0c0042, 0x0c0043) AM_DEVREADWRITE8("aciahost", acia6850_device, data_r, data_w, 0x00ff)
172	172	AM_RANGE(0x0c0080, 0x0c0081) AM_DEVREADWRITE8("aciaterm", acia6850_device, status_r, control_w, 0xff00)
173	173	AM_RANGE(0x0c0082, 0x0c0083) AM_DEVREADWRITE8("aciaterm", acia6850_device, data_r, data_w, 0xff00)
174	174	AM_RANGE(0x0c0100, 0x0c0101) AM_DEVREADWRITE8("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
175	175	AM_RANGE(0x0c0102, 0x0c0103) AM_DEVREADWRITE8("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
176		AM_RANGE(0x0c0400, 0x0c042f) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
177		AM_RANGE(0x0e0000, 0x0e0035) AM_DEVREADWRITE8("pit", pit68230_device, data_r, data_w, 0x00ff)
	176	AM_RANGE(0x0c0400, 0x0c042f) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
	177	AM_RANGE(0x0e0000, 0x0e0035) AM_DEVREADWRITE8("pit", pit68230_device, data_r, data_w, 0x00ff)
178	178	// AM_RANGE(0x0e0200, 0x0e0380) AM_READWRITE(fpu_r, fpu_w) /* optional FPCP 68881 FPU interface */
179	179	// AM_RANGE(0x100000, 0xfeffff) /* VMEbus Rev B addresses (24 bits) */
180	180	// AM_RANGE(0xff0000, 0xffffff) /* VMEbus Rev B addresses (16 bits) */
r248551	r248552
190	190	}
191	191
192	192	READ16_MEMBER(force68k_state::bootvect_r)
193		{
194		return m_sysrom[offset];
	193	{
	194	return m_sysrom[offset];
195	195	}
196	196
197	197	WRITE_LINE_MEMBER(force68k_state::write_aciahost_clock)
198		{
199		m_aciahost->write_txc(state);
	198	{
	199	m_aciahost->write_txc(state);
200	200	m_aciahost->write_rxc(state);
201	201	}
202	202
203	203	WRITE_LINE_MEMBER(force68k_state::write_aciaterm_clock)
204		{
205		m_aciaterm->write_txc(state);
	204	{
	205	m_aciaterm->write_txc(state);
206	206	m_aciaterm->write_rxc(state);
207	207	}
208	208
209	209	WRITE_LINE_MEMBER(force68k_state::write_aciaremt_clock)
210		{
211		m_aciaremt->write_txc(state);
	210	{
	211	m_aciaremt->write_txc(state);
212	212	m_aciaremt->write_rxc(state);
213	213	}
214	214
215	215	static MACHINE_CONFIG_START( fccpu1, force68k_state )
216	216	/* basic machine hardware */
217		MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz / 2)
	217	MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz / 2)
218	218	MCFG_CPU_PROGRAM_MAP(force68k_mem)
219	219
220		/* P3/Host Port config */
	220	/* P3/Host Port config */
221	221	MCFG_DEVICE_ADD("aciahost", ACIA6850, 0)
222		MCFG_DEVICE_ADD("aciahost_clock", CLOCK, ACIA_CLOCK)
	222	MCFG_DEVICE_ADD("aciahost_clock", CLOCK, ACIA_CLOCK)
223	223	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciahost_clock))
224	224
225		/* P4/Terminal Port config */
	225	/* P4/Terminal Port config */
226	226	MCFG_DEVICE_ADD("aciaterm", ACIA6850, 0)
227	227
228	228	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
r248551	r248552
232	232	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_rxd))
233	233	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_cts))
234	234
235		MCFG_DEVICE_ADD("aciaterm_clock", CLOCK, ACIA_CLOCK)
	235	MCFG_DEVICE_ADD("aciaterm_clock", CLOCK, ACIA_CLOCK)
236	236	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
237	237
238		/* P5/Remote Port config */
	238	/* P5/Remote Port config */
239	239	MCFG_DEVICE_ADD("aciaremt", ACIA6850, 0)
240	240
241	241	#define PRINTER 0
r248551	r248552
246	246	MCFG_RS232_PORT_ADD("rs232rmt", default_rs232_devices, "printer")
247	247	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_rxd))
248	248	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_cts))
249		#endif
	249	#endif
250	250
251		MCFG_DEVICE_ADD("aciaremt_clock", CLOCK, ACIA_CLOCK)
	251	MCFG_DEVICE_ADD("aciaremt_clock", CLOCK, ACIA_CLOCK)
252	252	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
253	253
254	254	/* RTC Real Time Clock device */
255	255	MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
256	256
257	257	/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
258		MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
	258	MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
259	259
260	260	MACHINE_CONFIG_END
261	261
r248551	r248552
291	291	ROM_START( fccpu1 )
292	292	ROM_REGION(0x1000000, "maincpu", 0)
293	293
294		ROM_LOAD16_BYTE( "fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC(3ac6f08f) SHA1(502f6547b508d8732bd68bbbb2402d8c30fefc3b) )
295		ROM_LOAD16_BYTE( "fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC(035315fb) SHA1(90dc44d9c25d28428233e6846da6edce2d69e440) )
296		/* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
	294	ROM_LOAD16_BYTE( "fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC(3ac6f08f) SHA1(502f6547b508d8732bd68bbbb2402d8c30fefc3b) )
	295	ROM_LOAD16_BYTE( "fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC(035315fb) SHA1(90dc44d9c25d28428233e6846da6edce2d69e440) )
	296	/* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
297	297	from a CPU-1 board so some features might be missing or different)
298	298	---------------------------------------------------------------------------
299	299	BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
r248551	r248552
309	309	GT <address> <CR> Exec prog: temporary breakpoint
310	310	HE<CR> Help; display monitor commands
311	311	LO [n] [;<options] <CR> Load Object file
312		MD <address> [<count» <CR> Memory Display
313		MM <address> [<data» [;<options» <CR> Memory Modify
	312	MD <address> [<count?? <CR> Memory Display
	313	MM <address> [<data?? [;<options?? <CR> Memory Modify
314	314	MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
315	315	NOBR [<address> ... ] <CR> Remove Breakpoint
316	316	NOPA <CR> Printer Detach (Centronics on PIT/P2)
r248551	r248552
318	318	PA <CR> Printer Attach (Centronics on PIT/P2)
319	319	PF[n] <CR> Set/display Port Format
320	320	RM <CR> Register Modify
321		TM [<exit character» <CR> Transparent Mode
	321	TM [<exit character?? <CR> Transparent Mode
322	322	TR [<count] <CR> Trace
323	323	TT <address> <CR> Trace: temporary breakpoint
324	324	VE [n] [<string] <CR> Verify memory/object file

trunk/src/mess/drivers/hh_sm510.c
r248551	r248552
57	57	{
58	58	// zerofill
59	59	m_inp_mux = 0;
60		// m_inp_lines = 0;
	60	// m_inp_lines = 0;
61	61	memset(m_lcd_output_cache, ~0, sizeof(m_lcd_output_cache));
62	62
63	63	// register for savestates
r248551	r248552
149	149	Konami Top Gun
150	150	* PCB label BH003
151	151	* Sharp SM510 under epoxy (die label CMS54C, KMS598)
152
	152
153	153	The ROM listing "BH003 Top Gun" from patent US5137277 is identical to the
154	154	released version, except for 2 probable bit errors and filler bytes. Unused
155	155	pages list data too, of what looks like assembler leftover garbage.

trunk/src/mess/drivers/hp64k.c
r248551	r248552
6	6	// ***************************************
7	7	//
8	8	// Documentation used for this driver:
9		// [1] HP, manual 64100-90910, dec 83 rev. - Model 64100A mainframe service manual
	9	// [1] HP, manual 64100-90910, dec 83 rev. - Model 64100A mainframe service manual
10	10	// [2] HP, manual 64941-90902, apr 83 rev. - Model 64941A Flexible disc (Floppy) drive
11	11	// controller service manual
12	12	//
13	13	// A 64100A system ("mainframe" in HP docs) is built around a 13 slot card cage.
14	14	// The first 4 slots are reserved for specific card types:
15		// J1 I/O card
16		// J2 Display and RAM card
17		// J3 CPU card
18		// J4 Floppy interface card
	15	// J1 I/O card
	16	// J2 Display and RAM card
	17	// J3 CPU card
	18	// J4 Floppy interface card
19	19	//
20	20	// The rest of the slots are for CPU emulators, logic analyzers and so on (i.e. those
21	21	// cards doing the main functions of a development system).
r248551	r248552
35	35	// CPU card (64100-66521 or 64100-66532)
36	36	//
37	37	// This board holds the HP custom CPU with its massive heatsink, the BIOS roms and little else.
38		// U30 5061-3011 HP "hybrid" CPU @ 6.25 MHz
	38	// U30 5061-3011 HP "hybrid" CPU @ 6.25 MHz
39	39	// U8
40	40	// U9
41	41	// U10
r248551	r248552
43	43	// U18
44	44	// U19
45	45	// U20
46		// U21 2732 16kw of BIOS EPROMs
	46	// U21 2732 16kw of BIOS EPROMs
47	47	//
48	48	// **********
49	49	// I/O card (64100-66520)
r248551	r248552
59	59	// exponentially decaying envelope (a bell sound) whereas in the emulation it's inside a
60	60	// simple rectangular envelope.
61	61	//
62		//*U20 HP "PHI" Custom HP-IB interface microcontroller
63		//*U28 i8251 RS232 UART
	62	//*U20 HP "PHI" Custom HP-IB interface microcontroller
	63	//*U28 i8251 RS232 UART
64	64	//
65	65	// **********
66	66	// Display card (64100-66530)
r248551	r248552
72	72	// CRTC is designed to refresh the whole DRAM in parallel. For some mysterious reason the first
73	73	// display row is always blanked (its 40 words of RAM are even used for the stack!).
74	74	//
75		// U33 i8275 CRT controller
76		// U60 2716 Character generator ROM
	75	// U33 i8275 CRT controller
	76	// U60 2716 Character generator ROM
77	77	// U23-U30
78		// U38-U45 HM4864 64 kw of DRAM
	78	// U38-U45 HM4864 64 kw of DRAM
79	79	//
80	80	// **********
81	81	// Floppy I/F card (64941-66501)
r248551	r248552
87	87	// I tried to reverse engineer the FSM by looking at the schematics and applying some sensible
88	88	// assumptions. Then I did a sort of "clean room" re-implementation. It appears to work correctly.
89	89	//
90		// U4 FD1791A Floppy disk controller
	90	// U4 FD1791A Floppy disk controller
91	91	//
92	92	// A brief summary of the reverse-engineered interface of this card follows.
93	93	//
r248551	r248552
162	162	#define BIT_MASK(n) (1U << (n))
163	163
164	164	// Macros to clear/set single bits
165		#define BIT_CLR(w , n) ((w) &= ~BIT_MASK(n))
166		#define BIT_SET(w , n) ((w) \|= BIT_MASK(n))
	165	#define BIT_CLR(w , n) ((w) &= ~BIT_MASK(n))
	166	#define BIT_SET(w , n) ((w) \|= BIT_MASK(n))
167	167
168	168	class hp64k_state : public driver_device
169	169	{
r248551	r248552
256	256	UINT8 m_slot_map;
257	257
258	258	// Floppy I/F
259		UINT8 m_floppy_in_latch_msb; // U23
260		UINT8 m_floppy_in_latch_lsb; // U38
261		UINT8 m_floppy_out_latch_msb; // U22
262		UINT8 m_floppy_out_latch_lsb; // U37
263		UINT8 m_floppy_if_ctrl; // U24
	259	UINT8 m_floppy_in_latch_msb; // U23
	260	UINT8 m_floppy_in_latch_lsb; // U38
	261	UINT8 m_floppy_out_latch_msb; // U22
	262	UINT8 m_floppy_out_latch_lsb; // U37
	263	UINT8 m_floppy_if_ctrl; // U24
264	264	bool m_floppy_dmaen;
265	265	bool m_floppy_dmai;
266	266	bool m_floppy_mdci;
r248551	r248552
268	268	bool m_floppy_drq;
269	269	bool m_floppy0_wpt;
270	270	bool m_floppy1_wpt;
271		UINT8 m_floppy_drv_ctrl; // U39
272		UINT8 m_floppy_status; // U25
	271	UINT8 m_floppy_drv_ctrl; // U39
	272	UINT8 m_floppy_status; // U25
273	273
274	274	typedef enum {
275	275	HP64K_FLPST_IDLE,
r248551	r248552
293	293	static ADDRESS_MAP_START(cpu_io_map , AS_IO , 16 , hp64k_state)
294	294	// PA = 0, IC = [0..3]
295	295	// Keyboard input
296		AM_RANGE(HP_MAKE_IOADDR(0 , 0) , HP_MAKE_IOADDR(0 , 3)) AM_READ(hp64k_kb_r)
	296	AM_RANGE(HP_MAKE_IOADDR(0 , 0) , HP_MAKE_IOADDR(0 , 3)) AM_READ(hp64k_kb_r)
297	297	// PA = 2, IC = [0..3]
298	298	// Line sync interrupt clear/watchdog reset
299		AM_RANGE(HP_MAKE_IOADDR(2 , 0) , HP_MAKE_IOADDR(2 , 3)) AM_READWRITE(hp64k_deltat_r , hp64k_deltat_w)
	299	AM_RANGE(HP_MAKE_IOADDR(2 , 0) , HP_MAKE_IOADDR(2 , 3)) AM_READWRITE(hp64k_deltat_r , hp64k_deltat_w)
300	300	// PA = 4, IC = [0..3]
301	301	// Floppy I/F
302		AM_RANGE(HP_MAKE_IOADDR(4 , 0) , HP_MAKE_IOADDR(4 , 3)) AM_READWRITE(hp64k_flp_r , hp64k_flp_w)
	302	AM_RANGE(HP_MAKE_IOADDR(4 , 0) , HP_MAKE_IOADDR(4 , 3)) AM_READWRITE(hp64k_flp_r , hp64k_flp_w)
303	303	// PA = 6, IC = [0..3]
304	304	// Read from USART
305		AM_RANGE(HP_MAKE_IOADDR(6 , 0) , HP_MAKE_IOADDR(6 , 3)) AM_READ(hp64k_usart_r)
	305	AM_RANGE(HP_MAKE_IOADDR(6 , 0) , HP_MAKE_IOADDR(6 , 3)) AM_READ(hp64k_usart_r)
306	306	// PA = 7, IC = 2
307	307	// Rear-panel switches
308		AM_RANGE(HP_MAKE_IOADDR(7 , 2) , HP_MAKE_IOADDR(7 , 2)) AM_READ(hp64k_rear_sw_r)
	308	AM_RANGE(HP_MAKE_IOADDR(7 , 2) , HP_MAKE_IOADDR(7 , 2)) AM_READ(hp64k_rear_sw_r)
309	309	// PA = 9, IC = [0..3]
310	310	// Beeper control & interrupt status read
311		AM_RANGE(HP_MAKE_IOADDR(9 , 0) , HP_MAKE_IOADDR(9 , 3)) AM_WRITE(hp64k_beep_w)
	311	AM_RANGE(HP_MAKE_IOADDR(9 , 0) , HP_MAKE_IOADDR(9 , 3)) AM_WRITE(hp64k_beep_w)
312	312	// PA = 10, IC = [0..3]
313	313	// Slot selection
314	314	AM_RANGE(HP_MAKE_IOADDR(10 , 0) , HP_MAKE_IOADDR(10 , 3)) AM_WRITE(hp64k_slot_sel_w)
r248551	r248552
922	922	// column = [0..15]
923	923	// row = [0..7]
924	924	PORT_START("KEY0")
925		PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
926		PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
927		PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
928		PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
929		PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
930		PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
931		PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
932		PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
933		PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
	925	PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
	926	PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
	927	PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
	928	PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
	929	PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
	930	PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
	931	PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
	932	PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
	933	PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
934	934	PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_UNUSED)
935	935	PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_UNUSED)
936	936	PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
r248551	r248552
938	938	PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_UNUSED)
939	939	PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_UNUSED)
940	940	PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_UNUSED)
941		PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')
942		PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
	941	PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')
	942	PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
943	943	PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_UNUSED)
944	944	PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_UNUSED)
945	945	PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_UNUSED)
946	946	PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
947		PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
948		PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
949		PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
950		PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
951		PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
952		PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~')
953		PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('\\') PORT_CHAR('\|')
954		PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
	947	PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
	948	PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
	949	PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
	950	PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
	951	PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
	952	PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~')
	953	PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('\\') PORT_CHAR('\|')
	954	PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
955	955	PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_UNUSED)
956	956	PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_UNUSED)
957	957
958	958	PORT_START("KEY1")
959		PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
960		PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
961		PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
962		PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
963		PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
964		PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
	959	PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
	960	PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
	961	PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	962	PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
	963	PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
	964	PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
965	965	PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_UNUSED)
966	966	PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
967	967	PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_UNUSED)
968	968	PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_UNUSED)
969	969	PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_UNUSED)
970	970	PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
971		PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F9) PORT_NAME("RECALL")
972		PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F10) PORT_NAME("CLRLINE")
973		PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F11) PORT_NAME("CAPS")
974		PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F12) PORT_NAME("RESET")
975		PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F1) PORT_NAME("SK1")
976		PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F2) PORT_NAME("SK2")
	971	PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F9) PORT_NAME("RECALL")
	972	PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F10) PORT_NAME("CLRLINE")
	973	PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F11) PORT_NAME("CAPS")
	974	PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F12) PORT_NAME("RESET")
	975	PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F1) PORT_NAME("SK1")
	976	PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F2) PORT_NAME("SK2")
977	977	PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_UNUSED)
978		PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F3) PORT_NAME("SK3")
979		PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F4) PORT_NAME("SK4")
	978	PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F3) PORT_NAME("SK3")
	979	PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F4) PORT_NAME("SK4")
980	980	PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
981	981	PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_UNUSED)
982		PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F5) PORT_NAME("SK5")
983		PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F6) PORT_NAME("SK6")
984		PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F7) PORT_NAME("SK7")
	982	PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F5) PORT_NAME("SK5")
	983	PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F6) PORT_NAME("SK6")
	984	PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F7) PORT_NAME("SK7")
985	985	PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_UNUSED)
986		PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F8) PORT_NAME("SK8")
	986	PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F8) PORT_NAME("SK8")
987	987	PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_UNUSED)
988	988	PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_UNUSED)
989	989	PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_UNUSED)
990	990	PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_UNUSED)
991	991
992	992	PORT_START("KEY2")
993		PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	993	PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
994	994	PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_UNUSED)
995		PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
996		PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
997		PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
998		PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
999		PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
	995	PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
	996	PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
	997	PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
	998	PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
	999	PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
1000	1000	PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
1001	1001	PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_UNUSED)
1002		PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
1003		PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
	1002	PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
	1003	PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
1004	1004	PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
1005	1005	PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_UNUSED)
1006	1006	PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_UNUSED)
1007		PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_INSERT) PORT_NAME("INSCHAR")
1008		PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("DELCHAR")
	1007	PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_INSERT) PORT_NAME("INSCHAR")
	1008	PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("DELCHAR")
1009	1009	PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_UNUSED)
1010	1010	PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_UNUSED)
1011		PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
1012		PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
1013		PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
	1011	PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
	1012	PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
	1013	PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
1014	1014	PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
1015	1015	PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_UNUSED)
1016		PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
	1016	PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
1017	1017	PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_UNUSED)
1018	1018	PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_UNUSED)
1019		PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
1020		PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR('{')
1021		PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('_') PORT_CHAR(UCHAR_MAMEKEY(DEL))
1022		PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_NAME("ROLLUP")
1023		PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
1024		PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_PGDN) PORT_NAME("NEXTPG")
	1019	PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
	1020	PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR('{')
	1021	PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('_') PORT_CHAR(UCHAR_MAMEKEY(DEL))
	1022	PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_NAME("ROLLUP")
	1023	PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
	1024	PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_PGDN) PORT_NAME("NEXTPG")
1025	1025
1026	1026	PORT_START("KEY3")
1027	1027	PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_UNUSED)
r248551	r248552
1029	1029	PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_UNUSED)
1030	1030	PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_UNUSED)
1031	1031	PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_UNUSED)
1032		PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
1033		PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
	1032	PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
	1033	PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
1034	1034	PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
1035		PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
1036		PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
1037		PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
1038		PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
1039		PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}')
1040		PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
	1035	PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
	1036	PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
	1037	PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
	1038	PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
	1039	PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}')
	1040	PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
1041	1041	PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
1042	1042	PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
1043	1043	PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_UNUSED)
r248551	r248552
1057	1057	PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
1058	1058	PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_PGUP) PORT_NAME("PREVPG")
1059	1059
1060		PORT_START("rear_sw")
1061		PORT_DIPNAME(0x8000 , 0x8000 , "E9-6 jumper")
1062		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1063		PORT_DIPSETTING(0x8000 , DEF_STR(No))
1064		PORT_DIPNAME(0x4000 , 0x4000 , "E9-5 jumper")
1065		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1066		PORT_DIPSETTING(0x4000 , DEF_STR(No))
1067		PORT_DIPNAME(0x2000 , 0x2000 , "E9-4 jumper")
1068		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1069		PORT_DIPSETTING(0x2000 , DEF_STR(No))
1070		PORT_DIPNAME(0x1000 , 0x1000 , "E9-3 jumper")
1071		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1072		PORT_DIPSETTING(0x1000 , DEF_STR(No))
1073		PORT_DIPNAME(0x0800 , 0x0800 , "E9-2 jumper")
1074		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1075		PORT_DIPSETTING(0x0800 , DEF_STR(No))
1076		PORT_DIPNAME(0x0400 , 0x0400 , "E9-1 jumper")
1077		PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1078		PORT_DIPSETTING(0x0400 , DEF_STR(No))
1079		PORT_DIPNAME(0x0018 , 0x0000 , "System source")
1080		PORT_DIPLOCATION("S1:!7,!6")
1081		PORT_DIPSETTING(0x0000 , "Sys bus")
1082		PORT_DIPSETTING(0x0008 , "Local storage-talk only")
1083		PORT_DIPSETTING(0x0010 , "Local storage-addressable")
1084		PORT_DIPSETTING(0x0018 , "Performance verification")
1085		PORT_DIPNAME(0x0300 , 0x0000 , "Upper bus address (N/U)")
1086		PORT_DIPLOCATION("S1:!2,!1")
1087		PORT_DIPSETTING(0x0000 , "0")
1088		PORT_DIPSETTING(0x0100 , "1")
1089		PORT_DIPSETTING(0x0200 , "2")
1090		PORT_DIPSETTING(0x0300 , "3")
1091		PORT_DIPNAME(0x0007 , 0x0000 , "System bus address")
1092		PORT_DIPLOCATION("S1:!5,!4,!3")
1093		PORT_DIPSETTING(0x0000 , "0")
1094		PORT_DIPSETTING(0x0001 , "1")
1095		PORT_DIPSETTING(0x0002 , "2")
1096		PORT_DIPSETTING(0x0003 , "3")
1097		PORT_DIPSETTING(0x0004 , "4")
1098		PORT_DIPSETTING(0x0005 , "5")
1099		PORT_DIPSETTING(0x0006 , "6")
1100		PORT_DIPSETTING(0x0007 , "7")
1101		PORT_DIPNAME(0x0080 , 0x0000 , "RS232 mode")
1102		PORT_DIPLOCATION("S4 IO:!8")
1103		PORT_DIPSETTING(0x0000 , "Terminal")
1104		PORT_DIPSETTING(0x0080 , "Modem")
	1060	PORT_START("rear_sw")
	1061	PORT_DIPNAME(0x8000 , 0x8000 , "E9-6 jumper")
	1062	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1063	PORT_DIPSETTING(0x8000 , DEF_STR(No))
	1064	PORT_DIPNAME(0x4000 , 0x4000 , "E9-5 jumper")
	1065	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1066	PORT_DIPSETTING(0x4000 , DEF_STR(No))
	1067	PORT_DIPNAME(0x2000 , 0x2000 , "E9-4 jumper")
	1068	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1069	PORT_DIPSETTING(0x2000 , DEF_STR(No))
	1070	PORT_DIPNAME(0x1000 , 0x1000 , "E9-3 jumper")
	1071	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1072	PORT_DIPSETTING(0x1000 , DEF_STR(No))
	1073	PORT_DIPNAME(0x0800 , 0x0800 , "E9-2 jumper")
	1074	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1075	PORT_DIPSETTING(0x0800 , DEF_STR(No))
	1076	PORT_DIPNAME(0x0400 , 0x0400 , "E9-1 jumper")
	1077	PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
	1078	PORT_DIPSETTING(0x0400 , DEF_STR(No))
	1079	PORT_DIPNAME(0x0018 , 0x0000 , "System source")
	1080	PORT_DIPLOCATION("S1:!7,!6")
	1081	PORT_DIPSETTING(0x0000 , "Sys bus")
	1082	PORT_DIPSETTING(0x0008 , "Local storage-talk only")
	1083	PORT_DIPSETTING(0x0010 , "Local storage-addressable")
	1084	PORT_DIPSETTING(0x0018 , "Performance verification")
	1085	PORT_DIPNAME(0x0300 , 0x0000 , "Upper bus address (N/U)")
	1086	PORT_DIPLOCATION("S1:!2,!1")
	1087	PORT_DIPSETTING(0x0000 , "0")
	1088	PORT_DIPSETTING(0x0100 , "1")
	1089	PORT_DIPSETTING(0x0200 , "2")
	1090	PORT_DIPSETTING(0x0300 , "3")
	1091	PORT_DIPNAME(0x0007 , 0x0000 , "System bus address")
	1092	PORT_DIPLOCATION("S1:!5,!4,!3")
	1093	PORT_DIPSETTING(0x0000 , "0")
	1094	PORT_DIPSETTING(0x0001 , "1")
	1095	PORT_DIPSETTING(0x0002 , "2")
	1096	PORT_DIPSETTING(0x0003 , "3")
	1097	PORT_DIPSETTING(0x0004 , "4")
	1098	PORT_DIPSETTING(0x0005 , "5")
	1099	PORT_DIPSETTING(0x0006 , "6")
	1100	PORT_DIPSETTING(0x0007 , "7")
	1101	PORT_DIPNAME(0x0080 , 0x0000 , "RS232 mode")
	1102	PORT_DIPLOCATION("S4 IO:!8")
	1103	PORT_DIPSETTING(0x0000 , "Terminal")
	1104	PORT_DIPSETTING(0x0080 , "Modem")
1105	1105
1106		PORT_START("rs232_sw")
1107		PORT_DIPNAME(0xc0 , 0x00 , "Stop bits")
1108		PORT_DIPLOCATION("S4 IO:!2,!1")
1109		PORT_DIPSETTING(0x00 , "Invalid")
1110		PORT_DIPSETTING(0x40 , "1")
1111		PORT_DIPSETTING(0x80 , "1.5")
1112		PORT_DIPSETTING(0xc0 , "2")
1113		PORT_DIPNAME(0x20 , 0x00 , "Parity")
1114		PORT_DIPLOCATION("S4 IO:!3")
1115		PORT_DIPSETTING(0x00 , "Odd")
1116		PORT_DIPSETTING(0x20 , "Even")
1117		PORT_DIPNAME(0x10 , 0x00 , "Parity enable")
1118		PORT_DIPLOCATION("S4 IO:!4")
1119		PORT_DIPSETTING(0x00 , DEF_STR(No))
1120		PORT_DIPSETTING(0x10 , DEF_STR(Yes))
1121		PORT_DIPNAME(0x0c , 0x00 , "Char length")
1122		PORT_DIPLOCATION("S4 IO:!6,!5")
1123		PORT_DIPSETTING(0x00 , "5")
1124		PORT_DIPSETTING(0x04 , "6")
1125		PORT_DIPSETTING(0x08 , "7")
1126		PORT_DIPSETTING(0x0c , "8")
1127		PORT_DIPNAME(0x02 , 0x00 , "Baud rate factor")
1128		PORT_DIPLOCATION("S4 IO:!7")
1129		PORT_DIPSETTING(0x00 , "1x")
1130		PORT_DIPSETTING(0x02 , "16x")
	1106	PORT_START("rs232_sw")
	1107	PORT_DIPNAME(0xc0 , 0x00 , "Stop bits")
	1108	PORT_DIPLOCATION("S4 IO:!2,!1")
	1109	PORT_DIPSETTING(0x00 , "Invalid")
	1110	PORT_DIPSETTING(0x40 , "1")
	1111	PORT_DIPSETTING(0x80 , "1.5")
	1112	PORT_DIPSETTING(0xc0 , "2")
	1113	PORT_DIPNAME(0x20 , 0x00 , "Parity")
	1114	PORT_DIPLOCATION("S4 IO:!3")
	1115	PORT_DIPSETTING(0x00 , "Odd")
	1116	PORT_DIPSETTING(0x20 , "Even")
	1117	PORT_DIPNAME(0x10 , 0x00 , "Parity enable")
	1118	PORT_DIPLOCATION("S4 IO:!4")
	1119	PORT_DIPSETTING(0x00 , DEF_STR(No))
	1120	PORT_DIPSETTING(0x10 , DEF_STR(Yes))
	1121	PORT_DIPNAME(0x0c , 0x00 , "Char length")
	1122	PORT_DIPLOCATION("S4 IO:!6,!5")
	1123	PORT_DIPSETTING(0x00 , "5")
	1124	PORT_DIPSETTING(0x04 , "6")
	1125	PORT_DIPSETTING(0x08 , "7")
	1126	PORT_DIPSETTING(0x0c , "8")
	1127	PORT_DIPNAME(0x02 , 0x00 , "Baud rate factor")
	1128	PORT_DIPLOCATION("S4 IO:!7")
	1129	PORT_DIPSETTING(0x00 , "1x")
	1130	PORT_DIPSETTING(0x02 , "16x")
1131	1131
1132	1132	INPUT_PORTS_END
1133	1133
1134	1134	static SLOT_INTERFACE_START(hp64k_floppies)
1135		SLOT_INTERFACE("525dd" , FLOPPY_525_DD)
	1135	SLOT_INTERFACE("525dd" , FLOPPY_525_DD)
1136	1136	SLOT_INTERFACE_END
1137	1137
1138	1138	static MACHINE_CONFIG_START(hp64k , hp64k_state)
r248551	r248552
1145	1145	// Actual keyboard refresh rate should be between 1 and 2 kHz
1146	1146	MCFG_TIMER_DRIVER_ADD_PERIODIC("kb_timer" , hp64k_state , hp64k_kb_scan , attotime::from_hz(100))
1147	1147
1148		// Line sync timer. A line frequency of 50 Hz is assumed.
1149		MCFG_TIMER_DRIVER_ADD_PERIODIC("linesync_timer" , hp64k_state , hp64k_line_sync , attotime::from_hz(50))
	1148	// Line sync timer. A line frequency of 50 Hz is assumed.
	1149	MCFG_TIMER_DRIVER_ADD_PERIODIC("linesync_timer" , hp64k_state , hp64k_line_sync , attotime::from_hz(50))
1150	1150
1151	1151	// Clock = 25 MHz / 9 * (112/114)
1152	1152	MCFG_DEVICE_ADD("crtc" , I8275 , 2729045)
r248551	r248552
1160	1160	MCFG_SCREEN_REFRESH_RATE(60)
1161	1161	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
1162	1162
1163		MCFG_FD1791_ADD("fdc" , XTAL_4MHz / 4)
1164		MCFG_WD_FDC_FORCE_READY
1165		MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_intrq_w))
1166		MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_drq_w))
1167		MCFG_FLOPPY_DRIVE_ADD("fdc:0" , hp64k_floppies , "525dd" , floppy_image_device::default_floppy_formats)
1168		MCFG_SLOT_FIXED(true)
1169		MCFG_FLOPPY_DRIVE_ADD("fdc:1" , hp64k_floppies , "525dd" , floppy_image_device::default_floppy_formats)
1170		MCFG_SLOT_FIXED(true)
	1163	MCFG_FD1791_ADD("fdc" , XTAL_4MHz / 4)
	1164	MCFG_WD_FDC_FORCE_READY
	1165	MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_intrq_w))
	1166	MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_drq_w))
	1167	MCFG_FLOPPY_DRIVE_ADD("fdc:0" , hp64k_floppies , "525dd" , floppy_image_device::default_floppy_formats)
	1168	MCFG_SLOT_FIXED(true)
	1169	MCFG_FLOPPY_DRIVE_ADD("fdc:1" , hp64k_floppies , "525dd" , floppy_image_device::default_floppy_formats)
	1170	MCFG_SLOT_FIXED(true)
1171	1171
1172		MCFG_DEVICE_ADD("fdc_rdy0" , TTL74123 , 0)
1173		MCFG_TTL74123_CONNECTION_TYPE(TTL74123_NOT_GROUNDED_NO_DIODE)
1174		MCFG_TTL74123_RESISTOR_VALUE(RES_K(68.1))
1175		// Warning! Duration formula is not correct for LS123, actual capacitor is 10 uF
1176		MCFG_TTL74123_CAPACITOR_VALUE(CAP_U(16))
1177		MCFG_TTL74123_B_PIN_VALUE(1)
1178		MCFG_TTL74123_CLEAR_PIN_VALUE(1)
1179		MCFG_TTL74123_OUTPUT_CHANGED_CB(WRITE8(hp64k_state , hp64k_floppy0_rdy));
	1172	MCFG_DEVICE_ADD("fdc_rdy0" , TTL74123 , 0)
	1173	MCFG_TTL74123_CONNECTION_TYPE(TTL74123_NOT_GROUNDED_NO_DIODE)
	1174	MCFG_TTL74123_RESISTOR_VALUE(RES_K(68.1))
	1175	// Warning! Duration formula is not correct for LS123, actual capacitor is 10 uF
	1176	MCFG_TTL74123_CAPACITOR_VALUE(CAP_U(16))
	1177	MCFG_TTL74123_B_PIN_VALUE(1)
	1178	MCFG_TTL74123_CLEAR_PIN_VALUE(1)
	1179	MCFG_TTL74123_OUTPUT_CHANGED_CB(WRITE8(hp64k_state , hp64k_floppy0_rdy));
1180	1180
1181		MCFG_DEVICE_ADD("fdc_rdy1" , TTL74123 , 0)
1182		MCFG_TTL74123_CONNECTION_TYPE(TTL74123_NOT_GROUNDED_NO_DIODE)
1183		MCFG_TTL74123_RESISTOR_VALUE(RES_K(68.1))
1184		MCFG_TTL74123_CAPACITOR_VALUE(CAP_U(16))
1185		MCFG_TTL74123_B_PIN_VALUE(1)
1186		MCFG_TTL74123_CLEAR_PIN_VALUE(1)
1187		MCFG_TTL74123_OUTPUT_CHANGED_CB(WRITE8(hp64k_state , hp64k_floppy1_rdy));
	1181	MCFG_DEVICE_ADD("fdc_rdy1" , TTL74123 , 0)
	1182	MCFG_TTL74123_CONNECTION_TYPE(TTL74123_NOT_GROUNDED_NO_DIODE)
	1183	MCFG_TTL74123_RESISTOR_VALUE(RES_K(68.1))
	1184	MCFG_TTL74123_CAPACITOR_VALUE(CAP_U(16))
	1185	MCFG_TTL74123_B_PIN_VALUE(1)
	1186	MCFG_TTL74123_CLEAR_PIN_VALUE(1)
	1187	MCFG_TTL74123_OUTPUT_CHANGED_CB(WRITE8(hp64k_state , hp64k_floppy1_rdy));
1188	1188
1189		MCFG_SPEAKER_STANDARD_MONO("mono")
1190		MCFG_SOUND_ADD("beeper" , BEEP , 2500)
1191		MCFG_SOUND_ROUTE(ALL_OUTPUTS , "mono" , 1.00)
	1189	MCFG_SPEAKER_STANDARD_MONO("mono")
	1190	MCFG_SOUND_ADD("beeper" , BEEP , 2500)
	1191	MCFG_SOUND_ROUTE(ALL_OUTPUTS , "mono" , 1.00)
1192	1192
1193		MCFG_TIMER_DRIVER_ADD("beep_timer" , hp64k_state , hp64k_beeper_off);
	1193	MCFG_TIMER_DRIVER_ADD("beep_timer" , hp64k_state , hp64k_beeper_off);
1194	1194	MACHINE_CONFIG_END
1195	1195
1196	1196	ROM_START(hp64k)

trunk/src/mess/drivers/i7000.c
r248551	r248552
55	55	public:
56	56	i7000_state(const machine_config &mconfig, device_type type, const char *tag)
57	57	: driver_device(mconfig, type, tag),
58		m_maincpu(*this, "maincpu"),
59		m_card(*this, "cardslot"),
60		m_gfxdecode(*this, "gfxdecode"),
61		m_videoram(*this, "videoram")
62		{ }
	58	m_maincpu(*this, "maincpu"),
	59	m_card(*this, "cardslot"),
	60	m_gfxdecode(*this, "gfxdecode"),
	61	m_videoram(*this, "videoram")
	62	{ }
63	63
64	64	void video_start();
65	65	void machine_start();
r248551	r248552
92	92	{
93	93	UINT8 data = 0xff;
94	94
95		for (int i=0; i<40*25; i++){
96		m_bg_tilemap->mark_tile_dirty(i);
97		}
	95	for (int i=0; i<40*25; i++){
	96	m_bg_tilemap->mark_tile_dirty(i);
	97	}
98	98
99	99	if (m_row < 8)
100	100	{
r248551	r248552
108	108	/* Input ports */
109	109	static INPUT_PORTS_START( i7000 )
110	110	PORT_START("X0")
111		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1)
112		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("9") PORT_CODE(KEYCODE_9)
113		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
114		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC)
115		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K)
116		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N)
117		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("!") PORT_CHAR('!')
118		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ENTER") PORT_CODE(KEYCODE_ENTER)
	111	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1)
	112	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("9") PORT_CODE(KEYCODE_9)
	113	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
	114	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC)
	115	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K)
	116	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N)
	117	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("!") PORT_CHAR('!')
	118	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ENTER") PORT_CODE(KEYCODE_ENTER)
119	119
120	120	PORT_START("X1")
121		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2)
122		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0") PORT_CODE(KEYCODE_0)
123		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T)
124		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x9D")
125		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
126		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X)
127		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x8F")
128		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^R DC2") //0x12
	121	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2)
	122	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0") PORT_CODE(KEYCODE_0)
	123	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T)
	124	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x9D")
	125	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
	126	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X)
	127	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x8F")
	128	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^R DC2") //0x12
129	129
130	130	PORT_START("X2")
131		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3)
132		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("$ ^") PORT_CHAR('$') PORT_CHAR('^')
133		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R)
134		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S)
135		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0xA0")
136		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C)
137		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("- _") PORT_CODE(KEYCODE_MINUS)
138		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BACKSPACE") PORT_CODE(KEYCODE_BACKSPACE)
	131	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3)
	132	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("$ ^") PORT_CHAR('$') PORT_CHAR('^')
	133	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R)
	134	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S)
	135	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0xA0")
	136	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C)
	137	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("- _") PORT_CODE(KEYCODE_MINUS)
	138	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BACKSPACE") PORT_CODE(KEYCODE_BACKSPACE)
139	139
140	140	PORT_START("X3")
141		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4") PORT_CODE(KEYCODE_4)
142		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("% +") PORT_CHAR('%') PORT_CHAR('+')
143		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I)
144		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D)
145		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x9C")
146		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M)
147		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("]") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']')
148		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("@") PORT_CHAR('@')
	141	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4") PORT_CODE(KEYCODE_4)
	142	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("% +") PORT_CHAR('%') PORT_CHAR('+')
	143	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I)
	144	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D)
	145	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0x9C")
	146	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M)
	147	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("]") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']')
	148	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("@") PORT_CHAR('@')
149	149
150	150	PORT_START("X4")
151		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("5 *") PORT_CODE(KEYCODE_5)
152		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^U NAK") //0x15
153		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O)
154		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F)
155		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\| <") PORT_CHAR('<')
156		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(", ;") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR(';')
157		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
158		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^E ENQ") //0x05
	151	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("5 *") PORT_CODE(KEYCODE_5)
	152	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^U NAK") //0x15
	153	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O)
	154	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F)
	155	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\| <") PORT_CHAR('<')
	156	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(", ;") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR(';')
	157	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
	158	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^E ENQ") //0x05
159	159
160	160	PORT_START("X5")
161		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("6") PORT_CODE(KEYCODE_6)
162		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^O SI") //0x0F
163		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P)
164		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G)
165		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J)
166		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(".") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.')
167		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("#") PORT_CHAR('#')
168		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("{") PORT_CHAR('{')
	161	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("6") PORT_CODE(KEYCODE_6)
	162	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^O SI") //0x0F
	163	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P)
	164	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G)
	165	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J)
	166	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(".") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.')
	167	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("#") PORT_CHAR('#')
	168	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("{") PORT_CHAR('{')
169	169
170	170	PORT_START("X6")
171		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("7") PORT_CODE(KEYCODE_7)
172		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q)
173		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E)
174		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A)
175		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H)
176		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V)
177		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^L FF") //0x0C
178		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^T DC4") //0x14
	171	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("7") PORT_CODE(KEYCODE_7)
	172	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q)
	173	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E)
	174	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A)
	175	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H)
	176	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V)
	177	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^L FF") //0x0C
	178	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("^T DC4") //0x14
179	179
180	180	PORT_START("X7")
181		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8") PORT_CODE(KEYCODE_8)
182		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
183		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
184		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(">") PORT_CHAR('>')
185		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z)
186		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B)
187		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("SPACEBAR") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
188		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("}") PORT_CHAR('}')
	181	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8") PORT_CODE(KEYCODE_8)
	182	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
	183	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
	184	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(">") PORT_CHAR('>')
	185	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z)
	186	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B)
	187	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("SPACEBAR") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	188	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("}") PORT_CHAR('}')
189	189
190	190	PORT_START("DSW") /* DP01 */
191		PORT_DIPNAME( 0x80, 0x80, "1")
192		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
193		PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
194		PORT_DIPNAME( 0x40, 0x40, "2")
195		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
196		PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
197		PORT_DIPNAME( 0x20, 0x00, "3")
198		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
199		PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
200		PORT_DIPNAME( 0x10, 0x10, "4")
201		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
202		PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
203		PORT_DIPNAME( 0x08, 0x08, "5")
204		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
205		PORT_DIPSETTING( 0x08, DEF_STR( Yes ) )
206		PORT_DIPNAME( 0x04, 0x04, "6")
207		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
208		PORT_DIPSETTING( 0x04, DEF_STR( Yes ) )
209		PORT_DIPNAME( 0x02, 0x00, "7")
210		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
211		PORT_DIPSETTING( 0x02, DEF_STR( Yes ) )
212		PORT_DIPNAME( 0x01, 0x01, "8")
213		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
214		PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
	191	PORT_DIPNAME( 0x80, 0x80, "1")
	192	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	193	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
	194	PORT_DIPNAME( 0x40, 0x40, "2")
	195	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	196	PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
	197	PORT_DIPNAME( 0x20, 0x00, "3")
	198	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	199	PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
	200	PORT_DIPNAME( 0x10, 0x10, "4")
	201	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	202	PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
	203	PORT_DIPNAME( 0x08, 0x08, "5")
	204	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	205	PORT_DIPSETTING( 0x08, DEF_STR( Yes ) )
	206	PORT_DIPNAME( 0x04, 0x04, "6")
	207	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	208	PORT_DIPSETTING( 0x04, DEF_STR( Yes ) )
	209	PORT_DIPNAME( 0x02, 0x00, "7")
	210	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	211	PORT_DIPSETTING( 0x02, DEF_STR( Yes ) )
	212	PORT_DIPNAME( 0x01, 0x01, "8")
	213	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	214	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
215	215	INPUT_PORTS_END
216	216
217	217	DRIVER_INIT_MEMBER(i7000_state, i7000)
r248551	r248552
238	238	/*FIXME: we still need to figure out the proper memory map
239	239	for the maincpu and where the cartridge slot maps to. */
240	240	static ADDRESS_MAP_START(i7000_mem, AS_PROGRAM, 8, i7000_state)
241		AM_RANGE(0x0000, 0x0fff) AM_ROM AM_REGION("boot", 0)
242		AM_RANGE(0x2000, 0x2fff) AM_RAM AM_SHARE("videoram")
243		AM_RANGE(0x4000, 0xffff) AM_RAM
	241	AM_RANGE(0x0000, 0x0fff) AM_ROM AM_REGION("boot", 0)
	242	AM_RANGE(0x2000, 0x2fff) AM_RAM AM_SHARE("videoram")
	243	AM_RANGE(0x4000, 0xffff) AM_RAM
244	244	// AM_RANGE(0x4000, 0xbfff) AM_ROM AM_REGION("cardslot", 0)
245	245	ADDRESS_MAP_END
246	246
247	247	static ADDRESS_MAP_START( i7000_io , AS_IO, 8, i7000_state)
248	248	ADDRESS_MAP_UNMAP_HIGH
249	249	ADDRESS_MAP_GLOBAL_MASK (0xff)
250		// AM_RANGE(0x06, 0x06) AM_WRITE(i7000_io_?_w)
251		// AM_RANGE(0x08, 0x09) AM_WRITE(i7000_io_?_w) //printer perhaps?
252		// AM_RANGE(0x0c, 0x0c) AM_WRITE(i7000_io_?_w) //0x0C and 0x10 may be related to mem page swapping. (self-test "4. PAG")
253		// AM_RANGE(0x10, 0x10) AM_WRITE(i7000_io_?_w)
254		// AM_RANGE(0x14, 0x15) AM_WRITE(i7000_io_?_w)
	250	// AM_RANGE(0x06, 0x06) AM_WRITE(i7000_io_?_w)
	251	// AM_RANGE(0x08, 0x09) AM_WRITE(i7000_io_?_w) //printer perhaps?
	252	// AM_RANGE(0x0c, 0x0c) AM_WRITE(i7000_io_?_w) //0x0C and 0x10 may be related to mem page swapping. (self-test "4. PAG")
	253	// AM_RANGE(0x10, 0x10) AM_WRITE(i7000_io_?_w)
	254	// AM_RANGE(0x14, 0x15) AM_WRITE(i7000_io_?_w)
255	255
256	256	AM_RANGE(0x18, 0x1b) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
257	257
258		// AM_RANGE(0x1c, 0x1c) AM_WRITE(i7000_io_printer_data_w) //ASCII data
	258	// AM_RANGE(0x1c, 0x1c) AM_WRITE(i7000_io_printer_data_w) //ASCII data
259	259	AM_RANGE(0x1d, 0x1d) AM_READ_PORT("DSW")
260		// AM_RANGE(0x1e, 0x1e) AM_READWRITE(i7000_io_printer_status_r, i7000_io_?_w)
261		// AM_RANGE(0x1f, 0x1f) AM_WRITE(i7000_io_printer_strobe_w) //self-test routine writes 0x08 and 0x09 (it seems that bit 0 is the strobe and bit 3 is an enable signal)
262		// AM_RANGE(0x20, 0x21) AM_READWRITE(i7000_io_keyboard_r, i7000_io_keyboard_w)
	260	// AM_RANGE(0x1e, 0x1e) AM_READWRITE(i7000_io_printer_status_r, i7000_io_?_w)
	261	// AM_RANGE(0x1f, 0x1f) AM_WRITE(i7000_io_printer_strobe_w) //self-test routine writes 0x08 and 0x09 (it seems that bit 0 is the strobe and bit 3 is an enable signal)
	262	// AM_RANGE(0x20, 0x21) AM_READWRITE(i7000_io_keyboard_r, i7000_io_keyboard_w)
263	263
264	264	AM_RANGE( 0x20, 0x20 ) AM_DEVREADWRITE("i8279", i8279_device, data_r, data_w)
265	265	AM_RANGE( 0x21, 0x21 ) AM_DEVREADWRITE("i8279", i8279_device, status_r, cmd_w)
266	266
267		// AM_RANGE(0x24, 0x24) AM_READ(i7000_io_?_r)
268		// AM_RANGE(0x25, 0x25) AM_WRITE(i7000_io_?_w)
	267	// AM_RANGE(0x24, 0x24) AM_READ(i7000_io_?_r)
	268	// AM_RANGE(0x25, 0x25) AM_WRITE(i7000_io_?_w)
269	269
270		// AM_RANGE(0x28, 0x2d) AM_READWRITE(i7000_io_joystick_r, i7000_io_joystick_w)
	270	// AM_RANGE(0x28, 0x2d) AM_READWRITE(i7000_io_joystick_r, i7000_io_joystick_w)
271	271
272		// AM_RANGE(0x3b, 0x3b) AM_WRITE(i7000_io_?_w)
273		// AM_RANGE(0x66, 0x67) AM_WRITE(i7000_io_?_w)
274		// AM_RANGE(0xbb, 0xbb) AM_WRITE(i7000_io_?_w) //may be related to page-swapping...
	272	// AM_RANGE(0x3b, 0x3b) AM_WRITE(i7000_io_?_w)
	273	// AM_RANGE(0x66, 0x67) AM_WRITE(i7000_io_?_w)
	274	// AM_RANGE(0xbb, 0xbb) AM_WRITE(i7000_io_?_w) //may be related to page-swapping...
275	275	ADDRESS_MAP_END
276	276
277	277	DEVICE_IMAGE_LOAD_MEMBER( i7000_state, i7000_card )
r248551	r248552
358	358	MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
359	359	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
360	360
361		/* Programmable timer */
	361	/* Programmable timer */
362	362	MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
363		// MCFG_PIT8253_CLK0(XTAL_4MHz / 2) /* TODO: verify on PCB */
364		// MCFG_PIT8253_OUT0_HANDLER(WRITELINE(i7000_state,i7000_pit_out0))
365		// MCFG_PIT8253_CLK1(XTAL_4MHz / 2) /* TODO: verify on PCB */
366		// MCFG_PIT8253_OUT1_HANDLER(WRITELINE(i7000_state,i7000_pit_out1))
	363	// MCFG_PIT8253_CLK0(XTAL_4MHz / 2) /* TODO: verify on PCB */
	364	// MCFG_PIT8253_OUT0_HANDLER(WRITELINE(i7000_state,i7000_pit_out0))
	365	// MCFG_PIT8253_CLK1(XTAL_4MHz / 2) /* TODO: verify on PCB */
	366	// MCFG_PIT8253_OUT1_HANDLER(WRITELINE(i7000_state,i7000_pit_out1))
367	367	MCFG_PIT8253_CLK2(XTAL_4MHz / 2) /* TODO: verify on PCB */
368	368	MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("speaker", speaker_sound_device, level_w))
369	369

trunk/src/mess/drivers/icatel.c
r248551	r248552
2	2	// copyright-holders: Felipe Sanches
3	3	/***************************************************************************
4	4
5		icatel - Brazilian public payphone
6		manufactured by icatel http://www.icatel.com.br/
	5	icatel - Brazilian public payphone
	6	manufactured by icatel http://www.icatel.com.br/
7	7
8		Partial schematics (drawn based on PCB inspection) available at:
9		https://github.com/garoa/Icatel/blob/master/doc/icatel.pdf
	8	Partial schematics (drawn based on PCB inspection) available at:
	9	https://github.com/garoa/Icatel/blob/master/doc/icatel.pdf
10	10
11		Driver by Felipe Sanches <juca@members.fsf.org>
	11	Driver by Felipe Sanches <juca@members.fsf.org>
12	12
13		Changelog:
	13	Changelog:
14	14
15		2014 DEC 14 [Felipe Sanches]:
16		* Initial driver skeleton
	15	2014 DEC 14 [Felipe Sanches]:
	16	* Initial driver skeleton
17	17
18	18	***************************************************************************/
19	19
r248551	r248552
81	81	ADDRESS_MAP_END
82	82
83	83	static ADDRESS_MAP_START(i80c31_data, AS_DATA, 8, icatel_state)
84		// AM_RANGE(0x0056,0x005A) AM_READ(magic_string) /* This is a hack! */
	84	// AM_RANGE(0x0056,0x005A) AM_READ(magic_string) /* This is a hack! */
85	85	ADDRESS_MAP_END
86	86
87	87	DRIVER_INIT_MEMBER( icatel_state, icatel )
r248551	r248552
98	98
99	99	READ8_MEMBER(icatel_state::magic_string)
100	100	{
101		// logerror("read: magic_string, offset=%04X\n", offset);
	101	// logerror("read: magic_string, offset=%04X\n", offset);
102	102	char mstr[] = "TP-OK";
103	103	return mstr[offset%5];
104	104	}
r248551	r248552
108	108	switch (offset%4)
109	109	{
110	110	case 0: return 0xff;
111		case 1: return 0x7f;
	111	case 1: return 0x7f;
112	112	case 2: return 0xff;
113	113	case 3: return 0xff;
114	114	}
r248551	r248552
169	169	READ8_MEMBER(icatel_state::ci15_r)
170	170	{
171	171	/* TODO: Implement-me! */
172		// debugger_break(machine());
173		// logerror("read: ci15\n");
	172	// debugger_break(machine());
	173	// logerror("read: ci15\n");
174	174	return (1 << 3) \| (1 << 0);
175	175	}
176	176

trunk/src/mess/drivers/rainbow.c
r248551	r248552
1122	1122
1123	1123	void rainbow_state::hdc_reset()
1124	1124	{
1125		// printf(">> HARD DISC CONTROLLER RESET <<\n");
	1125	// printf(">> HARD DISC CONTROLLER RESET <<\n");
1126	1126	logerror(">> HARD DISC CONTROLLER RESET <<\n");
1127	1127
1128	1128	m_hdc->reset(); // NEW HDC
r248551	r248552
2025	2025
2026	2026	if (m_unit < 2)
2027	2027	{
2028		data = data \| 8; // MOTOR 0 (for A or B)
	2028	data = data \| 8; // MOTOR 0 (for A or B)
2029	2029	}
2030	2030	else
2031	2031	{
r248551	r248552
2370	2370	// - first generation hardware (introduced May '82) with ROM 04.03.11
2371	2371	// - inability to boot from hard disc (mind the inadequate PSU)
2372	2372	//----------------------------------------------------------------------------------------
2373		// AVAILABLE RAM: 64 K on board (versus 128 K on model 'B').
	2373	// AVAILABLE RAM: 64 K on board (versus 128 K on model 'B').
2374	2374
2375	2375	// Two compatible memory expansions were sold by DEC:
2376	2376	// (PCIXX-AA) : 64 K (usable on either Rainbow 100-A or 100-B) *
r248551	r248552
2379	2379
2380	2380	// * DEC changed the way signals are handled on J6 (memory connector) later:
2381	2381	// "Whether a PC100-A or PC100-B memory module is installed on the PC100-B system module
2382		// affects the functions the signals on 5 pins (29, 30, 32, 43, and 47) of the J6 connector
	2382	// affects the functions the signals on 5 pins (29, 30, 32, 43, and 47) of the J6 connector
2383	2383	// will perform." (from 'EK-RB100_TM_001 Addendum for PC100-A_PC100-B Dec.84' page 120).
2384	2384	//----------------------------------------------------------------------------------------
2385	2385	// KNOWN DIFFERENCES TO 100-B:
r248551	r248552
2396	2396	// SOCKETED LANGUAGE ROM (E91) with 1 single localization per ROM -
2397	2397	ROM_LOAD("23-092e4-00.bin", 0xFE000, 0x2000, NO_DUMP) // ROM (FE000-FFFFF) (E91) 8 K - English (?)
2398	2398	// See also MP-01491-00 - PC100A FIELD MAINTENANCE SET. Appendix A of EK-RB100 Rainbow
2399		// Technical Manual Addendum f.100A and 100B (Dec.84) lists 15 localizations / part numbers
	2399	// Technical Manual Addendum f.100A and 100B (Dec.84) lists 15 localizations / part numbers
2400	2400
2401		ROM_REGION(0x1000, "chargen", 0) // [E98] 2732 (4 K) EPROM
	2401	ROM_REGION(0x1000, "chargen", 0) // [E98] 2732 (4 K) EPROM
2402	2402	ROM_LOAD("23-020e3-00.bin", 0x0000, 0x1000, CRC(1685e452) SHA1(bc299ff1cb74afcededf1a7beb9001188fdcf02f))
2403	2403	ROM_END
2404	2404
r248551	r248552
2410	2410	ROM_START(rainbow)
2411	2411	ROM_REGION(0x100000, "maincpu", 0)
2412	2412
2413		// Note that the 'Field Maintenance Print Set 1984' also lists alternate revision 'A1' with
	2413	// Note that the 'Field Maintenance Print Set 1984' also lists alternate revision 'A1' with
2414	2414	// 23-063e3-00 (for chargen) and '23-074e5-00' / '23-073e5-00' for E5-01 / E5-02.
2415	2415
2416	2416	// Part numbers 22E5, 20E5 and 37E3 verified to match revision "B" (FCC ID : A0994Q - PC100 - B).
2417	2417
2418		// BOOT ROM
2419		ROM_LOAD("23-022e5-00.bin", 0xf0000, 0x4000, CRC(9d1332b4) SHA1(736306d2a36bd44f95a39b36ebbab211cc8fea6e))
	2418	// BOOT ROM
	2419	ROM_LOAD("23-022e5-00.bin", 0xf0000, 0x4000, CRC(9d1332b4) SHA1(736306d2a36bd44f95a39b36ebbab211cc8fea6e))
2420	2420	ROM_RELOAD(0xf4000, 0x4000)
2421	2421
2422		// LANGUAGE ROM
	2422	// LANGUAGE ROM
2423	2423	ROM_LOAD("23-020e5-00.bin", 0xf8000, 0x4000, CRC(8638712f) SHA1(8269b0d95dc6efbe67d500dac3999df4838625d8)) // German, French, English
2424	2424	//ROM_LOAD( "23-015e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Dutch, French, English
2425	2425	//ROM_LOAD( "23-016e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Finish, Swedish, English
2426		//ROM_LOAD( "23-017e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Danish, Norwegian, English
2427		//ROM_LOAD( "23-018e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Spanish, Italian, English
	2426	//ROM_LOAD( "23-017e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Danish, Norwegian, English
	2427	//ROM_LOAD( "23-018e5-00.bin", 0xf8000, 0x4000, NO_DUMP) // Spanish, Italian, English
2428	2428	ROM_RELOAD(0xfc000, 0x4000)
2429	2429
2430	2430	// CHARACTER GENERATOR (E3-03)
2431		ROM_REGION(0x1000, "chargen", 0)
	2431	ROM_REGION(0x1000, "chargen", 0)
2432	2432	ROM_LOAD("23-037e3.bin", 0x0000, 0x1000, CRC(1685e452) SHA1(bc299ff1cb74afcededf1a7beb9001188fdcf02f))
2433	2433	ROM_END
2434	2434
r248551	r248552
2443	2443	// A Readme from January 1985 mentions 'recent ROM changes for MASS 11' (a VAX word processor).
2444	2444	// It is likely that the sole differences between 5.05 and 5.03 affect terminal emulation.
2445	2445
2446		// FIXME: ROM names are * made up *.
	2446	// FIXME: ROM names are * made up *.
2447	2447	// Someone who knows the DEC naming conventions should correct them -
2448	2448	ROM_START(rainbow190)
2449	2449	ROM_REGION(0x100000, "maincpu", 0)
r248551	r248552
2452	2452	ROM_LOAD("dec190rom1.bin", 0xf8000, 0x4000, CRC(5ce59632) SHA1(d29793f7014c57a4e7cb77bbf6e84f9113635ed2))
2453	2453
2454	2454	ROM_RELOAD(0xfc000, 0x4000)
2455		ROM_REGION(0x1000, "chargen", 0)
	2455	ROM_REGION(0x1000, "chargen", 0)
2456	2456	ROM_LOAD("chargen.bin", 0x0000, 0x1000, CRC(1685e452) SHA1(bc299ff1cb74afcededf1a7beb9001188fdcf02f))
2457	2457	ROM_END
2458	2458	//----------------------------------------------------------------------------------------

trunk/src/mess/drivers/rambo.c
r248551	r248552
11	11	http://reprap.org/mediawiki/images/7/75/Rambo1-1-schematic.png
12	12
13	13	3d printers currently supported by this driver:
14		* Metamáquina 2
	14	* Metam??quina 2
15	15
16	16	3d printers known to use this board:
17	17	* TODO: list them all here
r248551	r248552
31	31	class rambo_state : public driver_device
32	32	{
33	33	public:
34		rambo_state(const machine_config &mconfig, device_type type, const char *tag)
35		: driver_device(mconfig, type, tag),
36		m_maincpu(*this, "maincpu")
37		{
38		}
	34	rambo_state(const machine_config &mconfig, device_type type, const char *tag)
	35	: driver_device(mconfig, type, tag),
	36	m_maincpu(*this, "maincpu")
	37	{
	38	}
39	39
40		UINT8 m_port_a;
41		UINT8 m_port_b;
42		UINT8 m_port_c;
43		UINT8 m_port_d;
44		UINT8 m_port_e;
45		UINT8 m_port_f;
46		UINT8 m_port_g;
47		UINT8 m_port_h;
48		UINT8 m_port_j;
49		UINT8 m_port_k;
50		UINT8 m_port_l;
51		required_device<avr8_device> m_maincpu;
	40	UINT8 m_port_a;
	41	UINT8 m_port_b;
	42	UINT8 m_port_c;
	43	UINT8 m_port_d;
	44	UINT8 m_port_e;
	45	UINT8 m_port_f;
	46	UINT8 m_port_g;
	47	UINT8 m_port_h;
	48	UINT8 m_port_j;
	49	UINT8 m_port_k;
	50	UINT8 m_port_l;
	51	required_device<avr8_device> m_maincpu;
52	52
53		DECLARE_READ8_MEMBER(port_r);
54		DECLARE_WRITE8_MEMBER(port_w);
	53	DECLARE_READ8_MEMBER(port_r);
	54	DECLARE_WRITE8_MEMBER(port_w);
55	55
56		DECLARE_DRIVER_INIT(rambo);
57		virtual void machine_start();
58		virtual void machine_reset();
	56	DECLARE_DRIVER_INIT(rambo);
	57	virtual void machine_start();
	58	virtual void machine_reset();
59	59	};
60	60
61	61	void rambo_state::machine_start()
r248551	r248552
64	64
65	65	READ8_MEMBER(rambo_state::port_r)
66	66	{
67		switch( offset )
68		{
69		case AVR8_IO_PORTA:
70		{
	67	switch( offset )
	68	{
	69	case AVR8_IO_PORTA:
	70	{
71	71	#if LOG_PORTS
72		printf("[%08X] Port A READ \n", m_maincpu->m_shifted_pc);
	72	printf("[%08X] Port A READ \n", m_maincpu->m_shifted_pc);
73	73	#endif
74		return m_port_a;
75		}
76		default:
77		break;
78		}
79		return 0;
	74	return m_port_a;
	75	}
	76	default:
	77	break;
	78	}
	79	return 0;
80	80	}
81	81
82	82	WRITE8_MEMBER(rambo_state::port_w)
83	83	{
84		switch( offset )
85		{
86		case AVR8_IO_PORTA:
87		{
88		if (data == m_port_a) break;
	84	switch( offset )
	85	{
	86	case AVR8_IO_PORTA:
	87	{
	88	if (data == m_port_a) break;
89	89
90	90	#if LOG_PORTS
91		UINT8 old_port_a = m_port_a;
92		UINT8 changed = data ^ old_port_a;
	91	UINT8 old_port_a = m_port_a;
	92	UINT8 changed = data ^ old_port_a;
93	93	#endif
94		m_port_a = data;
95		break;
96		}
97		default:
98		break;
99		}
	94	m_port_a = data;
	95	break;
	96	}
	97	default:
	98	break;
	99	}
100	100	}
101	101
102	102	/****************************************************\
r248551	r248552
104	104	\****************************************************/
105	105
106	106	static ADDRESS_MAP_START( rambo_prg_map, AS_PROGRAM, 8, rambo_state )
107		AM_RANGE(0x0000, 0x1FFFF) AM_ROM
	107	AM_RANGE(0x0000, 0x1FFFF) AM_ROM
108	108	ADDRESS_MAP_END
109	109
110	110	static ADDRESS_MAP_START( rambo_data_map, AS_DATA, 8, rambo_state )
111		AM_RANGE(0x0200, 0x21FF) AM_RAM /* ATMEGA2560 Internal SRAM */
	111	AM_RANGE(0x0200, 0x21FF) AM_RAM /* ATMEGA2560 Internal SRAM */
112	112	ADDRESS_MAP_END
113	113
114	114	static ADDRESS_MAP_START( rambo_io_map, AS_IO, 8, rambo_state )
115		AM_RANGE(AVR8_IO_PORTA, AVR8_IO_PORTL) AM_READWRITE( port_r, port_w )
	115	AM_RANGE(AVR8_IO_PORTA, AVR8_IO_PORTL) AM_READWRITE( port_r, port_w )
116	116	ADDRESS_MAP_END
117	117
118	118	/****************************************************\
r248551	r248552
125	125
126	126	void rambo_state::machine_reset()
127	127	{
128		m_port_a = 0;
129		m_port_b = 0;
130		m_port_c = 0;
131		m_port_d = 0;
132		m_port_e = 0;
133		m_port_f = 0;
134		m_port_g = 0;
135		m_port_h = 0;
136		m_port_j = 0;
137		m_port_k = 0;
138		m_port_l = 0;
	128	m_port_a = 0;
	129	m_port_b = 0;
	130	m_port_c = 0;
	131	m_port_d = 0;
	132	m_port_e = 0;
	133	m_port_f = 0;
	134	m_port_g = 0;
	135	m_port_h = 0;
	136	m_port_j = 0;
	137	m_port_k = 0;
	138	m_port_l = 0;
139	139	}
140	140
141	141	static MACHINE_CONFIG_START( rambo, rambo_state )
142	142
143		MCFG_CPU_ADD("maincpu", ATMEGA2560, MASTER_CLOCK)
144		MCFG_CPU_PROGRAM_MAP(rambo_prg_map)
145		MCFG_CPU_DATA_MAP(rambo_data_map)
146		MCFG_CPU_IO_MAP(rambo_io_map)
	143	MCFG_CPU_ADD("maincpu", ATMEGA2560, MASTER_CLOCK)
	144	MCFG_CPU_PROGRAM_MAP(rambo_prg_map)
	145	MCFG_CPU_DATA_MAP(rambo_data_map)
	146	MCFG_CPU_IO_MAP(rambo_io_map)
147	147
148		MCFG_CPU_AVR8_EEPROM("eeprom")
149		MCFG_CPU_AVR8_LFUSE(0xFF)
150		MCFG_CPU_AVR8_HFUSE(0xDA)
151		MCFG_CPU_AVR8_EFUSE(0xF4)
152		MCFG_CPU_AVR8_LOCK(0x0F)
	148	MCFG_CPU_AVR8_EEPROM("eeprom")
	149	MCFG_CPU_AVR8_LFUSE(0xFF)
	150	MCFG_CPU_AVR8_HFUSE(0xDA)
	151	MCFG_CPU_AVR8_EFUSE(0xF4)
	152	MCFG_CPU_AVR8_LOCK(0x0F)
153	153
154		/TODO: Add an ATMEGA32U2 for USB-Serial communications /
155		/TODO: Emulate the AD5206 digipot /
156		/*TODO: Emulate the A4982 stepper motor drivers and instantiate 5 of these here
157		for controlling the X, Y, Z, E1 (and optionally E2) motors */
158		/TODO: Simulate the heating elements /
159		/TODO: Implement the thermistor measurements /
	154	/TODO: Add an ATMEGA32U2 for USB-Serial communications /
	155	/TODO: Emulate the AD5206 digipot /
	156	/*TODO: Emulate the A4982 stepper motor drivers and instantiate 5 of these here
	157	for controlling the X, Y, Z, E1 (and optionally E2) motors */
	158	/TODO: Simulate the heating elements /
	159	/TODO: Implement the thermistor measurements /
160	160	MACHINE_CONFIG_END
161	161
162	162	ROM_START( metamaq2 )
163		ROM_REGION( 0x20000, "maincpu", 0 )
164		ROM_DEFAULT_BIOS("20131015")
	163	ROM_REGION( 0x20000, "maincpu", 0 )
	164	ROM_DEFAULT_BIOS("20131015")
165	165
166		ROM_SYSTEM_BIOS( 0, "20130619", "June 19th, 2013" )
167		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_06_19) */
168		ROMX_LOAD("repetier-fw-metamaquina2-2013-06-19.bin", 0x0000, 0x1000e, CRC(4279b178) SHA1(e4d3c9d6421287c980639c2df32d07b754adc8fc), ROM_BIOS(1))
	166	ROM_SYSTEM_BIOS( 0, "20130619", "June 19th, 2013" )
	167	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_06_19) */
	168	ROMX_LOAD("repetier-fw-metamaquina2-2013-06-19.bin", 0x0000, 0x1000e, CRC(4279b178) SHA1(e4d3c9d6421287c980639c2df32d07b754adc8fc), ROM_BIOS(1))
169	169
170		ROM_SYSTEM_BIOS( 1, "20130624", "June 24th, 2013" )
171		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_RC2_RAMBo_rev10e_2013_06_24) */
172		ROMX_LOAD("repetier-fw-metamaquina2-2013-06-24_mm2rc2_rambo_rev10e.bin", 0x0000, 0xcebc, CRC(82400a3c) SHA1(0781ce29406ce69b63edb93d776b9c081bed841e), ROM_BIOS(2))
	170	ROM_SYSTEM_BIOS( 1, "20130624", "June 24th, 2013" )
	171	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_RC2_RAMBo_rev10e_2013_06_24) */
	172	ROMX_LOAD("repetier-fw-metamaquina2-2013-06-24_mm2rc2_rambo_rev10e.bin", 0x0000, 0xcebc, CRC(82400a3c) SHA1(0781ce29406ce69b63edb93d776b9c081bed841e), ROM_BIOS(2))
173	173
174		ROM_SYSTEM_BIOS( 2, "20130625", "June 25th, 2013" )
175		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_06_25) */
176		ROMX_LOAD("repetier-fw-metamaquina2-2013-06-25.bin", 0x0000, 0x10076, CRC(e7e4db38) SHA1(0c307bb0a0ee4e9d38253936e7030d0efb3c1845), ROM_BIOS(3))
	174	ROM_SYSTEM_BIOS( 2, "20130625", "June 25th, 2013" )
	175	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_06_25) */
	176	ROMX_LOAD("repetier-fw-metamaquina2-2013-06-25.bin", 0x0000, 0x10076, CRC(e7e4db38) SHA1(0c307bb0a0ee4e9d38253936e7030d0efb3c1845), ROM_BIOS(3))
177	177
178		ROM_SYSTEM_BIOS( 3, "20130709", "July 9th, 2013" )
179		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_09) */
180		ROMX_LOAD("repetier-fw-metamaquina2-2013-07-09.bin", 0x0000, 0x10078, CRC(9a45509f) SHA1(3a2e6516b45cc0ea1aef039335b02208847aaebf), ROM_BIOS(4))
	178	ROM_SYSTEM_BIOS( 3, "20130709", "July 9th, 2013" )
	179	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_09) */
	180	ROMX_LOAD("repetier-fw-metamaquina2-2013-07-09.bin", 0x0000, 0x10078, CRC(9a45509f) SHA1(3a2e6516b45cc0ea1aef039335b02208847aaebf), ROM_BIOS(4))
181	181
182		ROM_SYSTEM_BIOS( 4, "20130712", "July 12th, 2013" )
183		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_12) */
184		ROMX_LOAD("repetier-fw-metamaquina2-2013-07-12.bin", 0x0000, 0x10184, CRC(9aeac87c) SHA1(c1441096553c214c12a34da87fa42cc3f0eaf74d), ROM_BIOS(5))
	182	ROM_SYSTEM_BIOS( 4, "20130712", "July 12th, 2013" )
	183	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_12) */
	184	ROMX_LOAD("repetier-fw-metamaquina2-2013-07-12.bin", 0x0000, 0x10184, CRC(9aeac87c) SHA1(c1441096553c214c12a34da87fa42cc3f0eaf74d), ROM_BIOS(5))
185	185
186		ROM_SYSTEM_BIOS( 5, "20130717", "July 17th, 2013" )
187		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_17) */
188		ROMX_LOAD("repetier-fw-metamaquina2-2013-07-17.bin", 0x0000, 0x10180, CRC(7c053ed0) SHA1(7abeabcbfdb411b6e681e2d0c9398c40b142f76b), ROM_BIOS(6))
	186	ROM_SYSTEM_BIOS( 5, "20130717", "July 17th, 2013" )
	187	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_07_17) */
	188	ROMX_LOAD("repetier-fw-metamaquina2-2013-07-17.bin", 0x0000, 0x10180, CRC(7c053ed0) SHA1(7abeabcbfdb411b6e681e2d0c9398c40b142f76b), ROM_BIOS(6))
189	189
190		ROM_SYSTEM_BIOS( 6, "20130806", "August 6th, 2013" )
191		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_06) */
192		ROMX_LOAD("repetier-fw-metamaquina2-2013-08-06.bin", 0x0000, 0x1017e, CRC(6aaf5a14) SHA1(93cebee8ab9eda9d81e70504b407268a198577f0), ROM_BIOS(7))
	190	ROM_SYSTEM_BIOS( 6, "20130806", "August 6th, 2013" )
	191	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_06) */
	192	ROMX_LOAD("repetier-fw-metamaquina2-2013-08-06.bin", 0x0000, 0x1017e, CRC(6aaf5a14) SHA1(93cebee8ab9eda9d81e70504b407268a198577f0), ROM_BIOS(7))
193	193
194		ROM_SYSTEM_BIOS( 7, "20130809", "August 9th, 2013" )
195		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_09) */
196		ROMX_LOAD("repetier-fw-metamaquina2-2013-08-09.bin", 0x0000, 0x1018a, CRC(ee53a011) SHA1(666d09fe69220a172528fe8d1c358e3ddaaa743a), ROM_BIOS(8))
	194	ROM_SYSTEM_BIOS( 7, "20130809", "August 9th, 2013" )
	195	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_09) */
	196	ROMX_LOAD("repetier-fw-metamaquina2-2013-08-09.bin", 0x0000, 0x1018a, CRC(ee53a011) SHA1(666d09fe69220a172528fe8d1c358e3ddaaa743a), ROM_BIOS(8))
197	197
198		ROM_SYSTEM_BIOS( 8, "20130822", "August 22nd, 2013" )
199		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_22) */
200		ROMX_LOAD("repetier-fw-metamaquina2-2013-08-22.bin", 0x0000, 0x1018a, CRC(70a5a3c9) SHA1(20e52ea7bf40e71020b815b9fb6385d880677927), ROM_BIOS(9))
	198	ROM_SYSTEM_BIOS( 8, "20130822", "August 22nd, 2013" )
	199	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_08_22) */
	200	ROMX_LOAD("repetier-fw-metamaquina2-2013-08-22.bin", 0x0000, 0x1018a, CRC(70a5a3c9) SHA1(20e52ea7bf40e71020b815b9fb6385d880677927), ROM_BIOS(9))
201	201
202		ROM_SYSTEM_BIOS( 9, "20130913", "September 13th, 2013" )
203		/* source code for this one is unavailable as it was an unreleased internal development build */
204		ROMX_LOAD("repetier-fw-metamaquina2-2013-09-13-devel.bin", 0x0000, 0x101bc, CRC(5e7c7933) SHA1(5b9bfe919daf705ad7a9a2de3cf4c51e3338ec47), ROM_BIOS(10))
	202	ROM_SYSTEM_BIOS( 9, "20130913", "September 13th, 2013" )
	203	/* source code for this one is unavailable as it was an unreleased internal development build */
	204	ROMX_LOAD("repetier-fw-metamaquina2-2013-09-13-devel.bin", 0x0000, 0x101bc, CRC(5e7c7933) SHA1(5b9bfe919daf705ad7a9a2de3cf4c51e3338ec47), ROM_BIOS(10))
205	205
206		ROM_SYSTEM_BIOS( 10, "20130920", "September 20th, 2013" )
207		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_09_20) */
208		ROMX_LOAD("repetier-fw-metamaquina2-2013-09-20.bin", 0x0000, 0x10384, CRC(48378e58) SHA1(513f0a0c65219875cc467420cc091e3489b58919), ROM_BIOS(11))
	206	ROM_SYSTEM_BIOS( 10, "20130920", "September 20th, 2013" )
	207	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_09_20) */
	208	ROMX_LOAD("repetier-fw-metamaquina2-2013-09-20.bin", 0x0000, 0x10384, CRC(48378e58) SHA1(513f0a0c65219875cc467420cc091e3489b58919), ROM_BIOS(11))
209	209
210		ROM_SYSTEM_BIOS( 11, "20131015", "October 15th, 2013" )
211		/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_10_15) */
212		ROMX_LOAD("repetier-fw-metamaquina2-2013-10-15.bin", 0x0000, 0x102c8, CRC(520134bd) SHA1(dfe2251aad06972f237eb4920ce14ccb32da5af0), ROM_BIOS(12))
	210	ROM_SYSTEM_BIOS( 11, "20131015", "October 15th, 2013" )
	211	/* SOURCE(https://github.com/Metamaquina/Repetier-Firmware/tree/MM2_2013_10_15) */
	212	ROMX_LOAD("repetier-fw-metamaquina2-2013-10-15.bin", 0x0000, 0x102c8, CRC(520134bd) SHA1(dfe2251aad06972f237eb4920ce14ccb32da5af0), ROM_BIOS(12))
213	213
214		/Arduino MEGA bootloader /
215		/* This is marked as a BAD_DUMP because we're not sure this is the bootloader we're actually using.
216		This is inherited from the Replicator 1 driver.
217		A proper dump would be good.
218		Also, it is not clear whether there's any difference in the bootloader
219		between the ATMEGA1280 and the ATMEGA2560 MCUs */
220		ROM_LOAD( "atmegaboot_168_atmega1280.bin", 0x1f000, 0x0f16, BAD_DUMP CRC(c041f8db) SHA1(d995ebf360a264cccacec65f6dc0c2257a3a9224) )
	214	/Arduino MEGA bootloader /
	215	/* This is marked as a BAD_DUMP because we're not sure this is the bootloader we're actually using.
	216	This is inherited from the Replicator 1 driver.
	217	A proper dump would be good.
	218	Also, it is not clear whether there's any difference in the bootloader
	219	between the ATMEGA1280 and the ATMEGA2560 MCUs */
	220	ROM_LOAD( "atmegaboot_168_atmega1280.bin", 0x1f000, 0x0f16, BAD_DUMP CRC(c041f8db) SHA1(d995ebf360a264cccacec65f6dc0c2257a3a9224) )
221	221
222		/* on-die 4kbyte eeprom */
223		ROM_REGION( 0x1000, "eeprom", ROMREGION_ERASEFF )
	222	/* on-die 4kbyte eeprom */
	223	ROM_REGION( 0x1000, "eeprom", ROMREGION_ERASEFF )
224	224	ROM_END
225	225
226	226	/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */

trunk/src/mess/drivers/rc759.c
r248551	r248552
472	472	AM_RANGE(0x056, 0x057) AM_NOP // in reality, access to sound and rtc is a bit more involved
473	473	AM_RANGE(0x05a, 0x05b) AM_DEVWRITE8("snd", sn76489a_device, write, 0x00ff)
474	474	AM_RANGE(0x05c, 0x05d) AM_READWRITE8(rtc_r, rtc_w, 0x00ff)
475		// AM_RANGE(0x060, 0x06f) AM_WRITE8(crt_control_w, 0x00ff)
	475	// AM_RANGE(0x060, 0x06f) AM_WRITE8(crt_control_w, 0x00ff)
476	476	AM_RANGE(0x070, 0x077) AM_MIRROR(0x08) AM_DEVREADWRITE8("ppi", i8255_device, read, write, 0x00ff)
477	477	AM_RANGE(0x080, 0x0ff) AM_READWRITE8(nvram_r, nvram_w, 0x00ff)
478	478	// AM_RANGE(0x100, 0x101) net
r248551	r248552
487	487	// AM_RANGE(0x28d, 0x28d) external printer control
488	488	AM_RANGE(0x28e, 0x28f) AM_READWRITE8(floppy_ack_r, floppy_reserve_w, 0x00ff)
489	489	AM_RANGE(0x290, 0x291) AM_WRITE8(floppy_release_w, 0x00ff)
490		// AM_RANGE(0x292, 0x293) AM_READWRITE8(printer_ack_r, printer_reserve_w, 0x00ff)
491		// AM_RANGE(0x294, 0x295) AM_WRITE8(printer_release_w, 0x00ff)
	490	// AM_RANGE(0x292, 0x293) AM_READWRITE8(printer_ack_r, printer_reserve_w, 0x00ff)
	491	// AM_RANGE(0x294, 0x295) AM_WRITE8(printer_release_w, 0x00ff)
492	492	AM_RANGE(0x300, 0x30f) AM_DEVREADWRITE8("isbx", isbx_slot_device, mcs0_r, mcs0_w, 0x00ff)
493	493	AM_RANGE(0x310, 0x31f) AM_DEVREADWRITE8("isbx", isbx_slot_device, mcs1_r, mcs1_w, 0x00ff)
494		// AM_RANGE(0x320, 0x321) isbx dma ack
495		// AM_RANGE(0x330, 0x331) isbx tc
	494	// AM_RANGE(0x320, 0x321) isbx dma ack
	495	// AM_RANGE(0x330, 0x331) isbx tc
496	496	ADDRESS_MAP_END
497	497
498	498
r248551	r248552
554	554	MCFG_I82730_SINT_HANDLER(DEVWRITELINE("pic", pic8259_device, ir4_w))
555	555
556	556	// keyboard
557		MCFG_DEVICE_ADD("keyb", GENERIC_KEYBOARD, 0)
558		MCFG_GENERIC_KEYBOARD_CB(WRITE8(rc759_state, keyb_put))
	557	MCFG_DEVICE_ADD("keyb", GENERIC_KEYBOARD, 0)
	558	MCFG_GENERIC_KEYBOARD_CB(WRITE8(rc759_state, keyb_put))
559	559
560	560	// cassette
561	561	MCFG_CASSETTE_ADD("cas")
r248551	r248552
584	584
585	585	// floppy disk controller
586	586	MCFG_WD2797_ADD("fdc", 1000000)
587		// MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE("pic", pic8259_device, ir0_w))
588		// MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu", i80186_cpu_device, drq1_w))
	587	// MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE("pic", pic8259_device, ir0_w))
	588	// MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu", i80186_cpu_device, drq1_w))
589	589
590	590	// floppy drives
591	591	MCFG_FLOPPY_DRIVE_ADD("fdc:0", rc759_floppies, "hd", floppy_image_device::default_floppy_formats)

trunk/src/mess/drivers/sdk80.c
r248551	r248552
29	29	#include "bus/rs232/rs232.h"
30	30	//#include "machine/ay31015.h"
31	31
32		#define I8251A_TAG "usart"
33		#define I8251A_BAUD_TAG "usart_baud"
34		#define RS232_TAG "rs232"
	32	#define I8251A_TAG "usart"
	33	#define I8251A_BAUD_TAG "usart_baud"
	34	#define RS232_TAG "rs232"
35	35
36	36	class sdk80_state : public driver_device
37	37	{
r248551	r248552
145	145	/* video hardware */
146	146	// 96364 crt controller
147	147
148		// MCFG_SCREEN_ADD("screen", RASTER)
149		// MCFG_SCREEN_REFRESH_RATE(60)
	148	// MCFG_SCREEN_ADD("screen", RASTER)
	149	// MCFG_SCREEN_REFRESH_RATE(60)
150	150	/* Video is blanked for 70 out of 262 scanlines per refresh cycle.
151	151	Each scanline is composed of 65 character times, 40 of which
152	152	are visible, and each character time is 7 dot times; a dot time
153	153	is 2 cycles of the fundamental 14.31818 MHz oscillator. The
154	154	total blanking time is about 4450 microseconds. */
155		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC((int) (70 * 65 * 7 * 2 / 14.31818)))
	155	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC((int) (70 * 65 * 7 * 2 / 14.31818)))
156	156	/* It would be nice if we could implement some sort of display
157	157	overscan here. */
158		// MCFG_SCREEN_SIZE(40 * 7, 24 * 8)
159		// MCFG_SCREEN_VISIBLE_AREA(0, 40 * 7 - 1, 0, 24 * 8 - 1)
160		// MCFG_SCREEN_UPDATE_DRIVER(sdk80_state, screen_update)
161		// MCFG_SCREEN_PALETTE("palette")
	158	// MCFG_SCREEN_SIZE(40 * 7, 24 * 8)
	159	// MCFG_SCREEN_VISIBLE_AREA(0, 40 * 7 - 1, 0, 24 * 8 - 1)
	160	// MCFG_SCREEN_UPDATE_DRIVER(sdk80_state, screen_update)
	161	// MCFG_SCREEN_PALETTE("palette")
162	162
163		// MCFG_GFXDECODE_ADD("gfxdecode", "palette", sdk80)
	163	// MCFG_GFXDECODE_ADD("gfxdecode", "palette", sdk80)
164	164
165		// MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
	165	// MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
166	166
167	167	// Video board UART
168		// MCFG_DEVICE_ADD( "hd6402", AY31015, 0 )
169		// MCFG_AY31015_TX_CLOCK(( XTAL_16MHz / 16 ) / 256)
170		// MCFG_AY31015_RX_CLOCK(( XTAL_16MHz / 16 ) / 256)
171		// MCFG_AY51013_READ_SI_CB(READ8(sdk80_state, nascom1_hd6402_si))
172		// MCFG_AY51013_WRITE_SO_CB(WRITE8(sdk80_state, nascom1_hd6402_so))
	168	// MCFG_DEVICE_ADD( "hd6402", AY31015, 0 )
	169	// MCFG_AY31015_TX_CLOCK(( XTAL_16MHz / 16 ) / 256)
	170	// MCFG_AY31015_RX_CLOCK(( XTAL_16MHz / 16 ) / 256)
	171	// MCFG_AY51013_READ_SI_CB(READ8(sdk80_state, nascom1_hd6402_si))
	172	// MCFG_AY51013_WRITE_SO_CB(WRITE8(sdk80_state, nascom1_hd6402_so))
173	173
174	174	/* Devices */
175		// MCFG_DEVICE_ADD("i8279", I8279, 3100000) // based on divider
176		// MCFG_I8279_OUT_IRQ_CB(INPUTLINE("maincpu", I8085_RST55_LINE)) // irq
177		// MCFG_I8279_OUT_SL_CB(WRITE8(sdk80_state, scanlines_w)) // scan SL lines
178		// MCFG_I8279_OUT_DISP_CB(WRITE8(sdk80_state, digit_w)) // display A&B
179		// MCFG_I8279_IN_RL_CB(READ8(sdk80_state, kbd_r)) // kbd RL lines
180		// MCFG_I8279_IN_SHIFT_CB(VCC) // Shift key
181		// MCFG_I8279_IN_CTRL_CB(VCC)
	175	// MCFG_DEVICE_ADD("i8279", I8279, 3100000) // based on divider
	176	// MCFG_I8279_OUT_IRQ_CB(INPUTLINE("maincpu", I8085_RST55_LINE)) // irq
	177	// MCFG_I8279_OUT_SL_CB(WRITE8(sdk80_state, scanlines_w)) // scan SL lines
	178	// MCFG_I8279_OUT_DISP_CB(WRITE8(sdk80_state, digit_w)) // display A&B
	179	// MCFG_I8279_IN_RL_CB(READ8(sdk80_state, kbd_r)) // kbd RL lines
	180	// MCFG_I8279_IN_SHIFT_CB(VCC) // Shift key
	181	// MCFG_I8279_IN_CTRL_CB(VCC)
182	182
183	183	//MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
184	184	//MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(sdk80_state, kbd_put))

trunk/src/mess/drivers/smc777.c
r248551	r248552
613	613	AM_RANGE(0x18, 0x19) AM_MIRROR(0xff00) AM_WRITE(mc6845_w)
614	614	AM_RANGE(0x1a, 0x1b) AM_MIRROR(0xff00) AM_READWRITE(key_r, key_w)
615	615	AM_RANGE(0x1c, 0x1c) AM_MIRROR(0xff00) AM_READWRITE(system_input_r, system_output_w)
616		// AM_RANGE(0x1d, 0x1d) system and control read, printer strobe write
617		// AM_RANGE(0x1e, 0x1f) rs232 irq control
	616	// AM_RANGE(0x1d, 0x1d) system and control read, printer strobe write
	617	// AM_RANGE(0x1e, 0x1f) rs232 irq control
618	618	AM_RANGE(0x20, 0x20) AM_MIRROR(0xff00) AM_READWRITE(display_reg_r, display_reg_w)
619	619	AM_RANGE(0x21, 0x21) AM_MIRROR(0xff00) AM_READWRITE(irq_mask_r, irq_mask_w)
620		// AM_RANGE(0x22, 0x22) printer output data
	620	// AM_RANGE(0x22, 0x22) printer output data
621	621	AM_RANGE(0x23, 0x23) AM_MIRROR(0xff00) AM_WRITE(border_col_w)
622		// AM_RANGE(0x24, 0x24) rtc write address
623		// AM_RANGE(0x25, 0x25) rtc read
624		// AM_RANGE(0x26, 0x26) rs232 #1
625		// AM_RANGE(0x28, 0x2c) fdc #2
626		// AM_RANGE(0x2d, 0x2f) rs232 #2
	622	// AM_RANGE(0x24, 0x24) rtc write address
	623	// AM_RANGE(0x25, 0x25) rtc read
	624	// AM_RANGE(0x26, 0x26) rs232 #1
	625	// AM_RANGE(0x28, 0x2c) fdc #2
	626	// AM_RANGE(0x2d, 0x2f) rs232 #2
627	627	AM_RANGE(0x30, 0x33) AM_MIRROR(0xff00) AM_READWRITE(fdc_r, fdc_w)
628	628	AM_RANGE(0x34, 0x34) AM_MIRROR(0xff00) AM_READWRITE(fdc_request_r, floppy_select_w)
629		// AM_RANGE(0x35, 0x37) rs232 #3
630		// AM_RANGE(0x38, 0x3b) cache disk unit
631		// AM_RANGE(0x3c, 0x3d) rgb superimposer
632		// AM_RANGE(0x40, 0x47) ieee-488
633		// AM_RANGE(0x48, 0x4f) hdd (winchester)
	629	// AM_RANGE(0x35, 0x37) rs232 #3
	630	// AM_RANGE(0x38, 0x3b) cache disk unit
	631	// AM_RANGE(0x3c, 0x3d) rgb superimposer
	632	// AM_RANGE(0x40, 0x47) ieee-488
	633	// AM_RANGE(0x48, 0x4f) hdd (winchester)
634	634	AM_RANGE(0x51, 0x51) AM_MIRROR(0xff00) AM_READ_PORT("JOY_1P") AM_WRITE(color_mode_w)
635	635	AM_RANGE(0x52, 0x52) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_WRITE(ramdac_w)
636	636	AM_RANGE(0x53, 0x53) AM_MIRROR(0xff00) AM_DEVWRITE("sn1", sn76489a_device, write)
637		// AM_RANGE(0x54, 0x59) vrt controller
638		// AM_RANGE(0x5a, 0x5b) ram banking
639		// AM_RANGE(0x70, 0x70) auto-start rom
640		// AM_RANGE(0x74, 0x74) ieee-488 rom
641		// AM_RANGE(0x75, 0x75) vrt controller rom
642		// AM_RANGE(0x7e, 0x7f) kanji rom
	637	// AM_RANGE(0x54, 0x59) vrt controller
	638	// AM_RANGE(0x5a, 0x5b) ram banking
	639	// AM_RANGE(0x70, 0x70) auto-start rom
	640	// AM_RANGE(0x74, 0x74) ieee-488 rom
	641	// AM_RANGE(0x75, 0x75) vrt controller rom
	642	// AM_RANGE(0x7e, 0x7f) kanji rom
643	643	AM_RANGE(0x80, 0xff) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(fbuf_r, fbuf_w)
644	644	ADDRESS_MAP_END
645	645

trunk/src/mess/drivers/tb303.c
r248551	r248552
28	28	{ }
29	29
30	30	required_device<timer_device> m_t3_off_timer;
31
	31
32	32	UINT8 m_ram[0xc00];
33	33	UINT16 m_ram_address;
34	34	bool m_ram_ce;
r248551	r248552
97	97	case 2: hi = 1; break;
98	98	case 3: hi = 2; break;
99	99	}
100
	100
101	101	if (m_ram_ce)
102	102	{
103	103	// _WE must be high(read mode) for address transitions
r248551	r248552
114	114	// MCU D,F,E: RAM address
115	115	m_port[offset] = data;
116	116	refresh_ram();
117
	117
118	118	// MCU D,F01: pitch data
119	119	//..
120	120	}
r248551	r248552
133	133	// MCU I0: RAM _WE
134	134	m_ram_we = (data & 1) ? false : true;
135	135	refresh_ram();
136
	136
137	137	// MCU I1: pitch data latch strobe
138	138	// MCU I2: gate signal
139	139
r248551	r248552
147	147	{
148	148	// 4*4 LED matrix from port G/H:
149	149	/*
150		0.0 D204 1.0 D211 2.0 D217 3.0 D205
151		0.1 D206 1.1 D213 2.1 D218 3.1 D207
152		0.2 D208 1.2 D215 2.2 D220 3.2 D210
153		0.3 D209 1.3 D216 2.3 D221 3.3 D212
	150	0.0 D204 1.0 D211 2.0 D217 3.0 D205
	151	0.1 D206 1.1 D213 2.1 D218 3.1 D207
	152	0.2 D208 1.2 D215 2.2 D220 3.2 D210
	153	0.3 D209 1.3 D216 2.3 D221 3.3 D212
154	154	*/
155	155	display_matrix(4, 4, m_port[NEC_UCOM4_PORTG], m_port[NEC_UCOM4_PORTH]);
156
	156
157	157	// todo: battery led
158	158	// todo: 4 more leds(see top-left part)
159	159	}
r248551	r248552
164	164	// MCU H: input/led mux
165	165	if (offset == NEC_UCOM4_PORTH)
166	166	m_inp_mux = data = data ^ 0xf;
167
	167
168	168	m_port[offset] = data;
169	169	update_leds();
170	170	}
r248551	r248552
253	253	void tb303_state::machine_start()
254	254	{
255	255	hh_ucom4_state::machine_start();
256
	256
257	257	// zerofill
258	258	memset(m_ram, 0, sizeof(m_ram));
259	259	m_ram_address = 0;
260	260	m_ram_ce = false;
261	261	m_ram_we = false;
262
	262
263	263	// register for savestates
264	264	save_item(NAME(m_ram));
265	265	save_item(NAME(m_ram_address));

trunk/src/mess/drivers/xbox.c
r248551	r248552
2	2	// copyright-holders:?
3	3	/***************************************************************************
4	4
5		XBOX (c) 2001 Microsoft
	5	XBOX (c) 2001 Microsoft
6	6
7		Skeleton driver
8
	7	Skeleton driver
	8
9	9	***************************************************************************/
10	10
11	11
r248551	r248552
64	64	static ADDRESS_MAP_START(xbox_map, AS_PROGRAM, 32, xbox_state)
65	65	AM_RANGE(0x00000000, 0x07ffffff) AM_RAM // 128 megabytes
66	66	AM_RANGE(0xf0000000, 0xf0ffffff) AM_RAM
67		// AM_RANGE(0xfd000000, 0xfdffffff) AM_RAM AM_READWRITE(geforce_r, geforce_w)
68		// AM_RANGE(0xfed00000, 0xfed003ff) AM_READWRITE(usbctrl_r, usbctrl_w)
69		// AM_RANGE(0xfe800000, 0xfe85ffff) AM_READWRITE(audio_apu_r, audio_apu_w)
70		// AM_RANGE(0xfec00000, 0xfec001ff) AM_READWRITE(audio_ac93_r, audio_ac93_w)
	67	// AM_RANGE(0xfd000000, 0xfdffffff) AM_RAM AM_READWRITE(geforce_r, geforce_w)
	68	// AM_RANGE(0xfed00000, 0xfed003ff) AM_READWRITE(usbctrl_r, usbctrl_w)
	69	// AM_RANGE(0xfe800000, 0xfe85ffff) AM_READWRITE(audio_apu_r, audio_apu_w)
	70	// AM_RANGE(0xfec00000, 0xfec001ff) AM_READWRITE(audio_ac93_r, audio_ac93_w)
71	71	AM_RANGE(0xff000000, 0xff07ffff) AM_ROM AM_REGION("bios", 0) AM_MIRROR(0x00f80000)
72	72	ADDRESS_MAP_END
73	73
74	74	static ADDRESS_MAP_START(xbox_map_io, AS_IO, 32, xbox_state)
75		// AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
76		// AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
77		// AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
78		// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
79		// AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
80		// AM_RANGE(0x4000, 0x40ff) AM_READWRITE(mediaboard_r, mediaboard_w)
81		// AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
82		// AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
83		// AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w)
	75	// AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
	76	// AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
	77	// AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
	78	// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
	79	// AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
	80	// AM_RANGE(0x4000, 0x40ff) AM_READWRITE(mediaboard_r, mediaboard_w)
	81	// AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
	82	// AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
	83	// AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w)
84	84	ADDRESS_MAP_END
85	85
86	86	static INPUT_PORTS_START( xbox )
r248551	r248552
161	161	MCFG_CPU_ADD("maincpu", PENTIUM3, 733333333/CPU_DIV) /* Wrong! family 6 model 8 stepping 10 */
162	162	MCFG_CPU_PROGRAM_MAP(xbox_map)
163	163	MCFG_CPU_IO_MAP(xbox_map_io)
164		// MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(chihiro_state, irq_callback)
	164	// MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(chihiro_state, irq_callback)
165	165
166	166	/* video hardware */
167	167	MCFG_SCREEN_ADD("screen", RASTER)
r248551	r248552
193	193	ROM_REGION( 0x200, "mcpx", 0 )
194	194	ROM_LOAD( "mcpx_1_0.bin", 0, 0x200, CRC(f31429fc) SHA1(a9ecbf8896d10db81594923e485862aa3aac7b58) )
195	195	ROM_LOAD( "mcpx_1_1.bin", 0, 0x200, CRC(94ce376b) SHA1(6c875f17f773aaec51eb434068bb6c657c4343c0) )
196
	196
197	197	ROM_REGION( 0x80000, "bios", 0)
198		ROM_LOAD( "xbox-5530.bin", 0x000000, 0x040000, CRC(9569c4d3) SHA1(40fa73277013be3168135e1768b09623a987ff63) )
199		ROM_LOAD( "xbox-5713.bin", 0x040000, 0x040000, CRC(58fd8173) SHA1(8b7ccc4648ccd78cdb7b65cfca09621eaf2d4238) )
	198	ROM_LOAD( "xbox-5530.bin", 0x000000, 0x040000, CRC(9569c4d3) SHA1(40fa73277013be3168135e1768b09623a987ff63) )
	199	ROM_LOAD( "xbox-5713.bin", 0x040000, 0x040000, CRC(58fd8173) SHA1(8b7ccc4648ccd78cdb7b65cfca09621eaf2d4238) )
200	200	ROM_COPY( "mcpx", 0, 0x7fe00, 0x200 )
201
202	201
	202
203	203	ROM_REGION( 0x1000000, "tbp", 0 ) // To Be Processed, of course
204	204	ROM_LOAD( "3944_1024k.bin", 0x000000, 0x100000, CRC(32a9ecb6) SHA1(67054fc88bda94e33e86f1b19be60efec0724fb6) )
205		ROM_LOAD( "4034_1024k.bin", 0x000000, 0x100000, CRC(0d6fc88f) SHA1(ab676b712204fb1728bf89f9cd541a8f5a64ab97) )
206		ROM_LOAD( "4134_1024k.bin", 0x000000, 0x100000, CRC(49d8055a) SHA1(d46cef771a63dc8024fe36d7ab5b959087ac999f) )
207		ROM_LOAD( "4817_1024k.bin", 0x000000, 0x100000, CRC(3f30863a) SHA1(dc955bd4d3ca71e01214a49e5d0aba615270c03c) )
208		ROM_LOAD( "5101_256k.bin", 0x000000, 0x040000, CRC(e8a9224e) SHA1(5108e1025f48071c07a6823661d708c66dee97a9) )
209		ROM_LOAD( "5838_256k.bin", 0x000000, 0x040000, CRC(5be2413d) SHA1(b9489e883c650b5e5fe2f83a32237dbf74f0e9f1) )
	205	ROM_LOAD( "4034_1024k.bin", 0x000000, 0x100000, CRC(0d6fc88f) SHA1(ab676b712204fb1728bf89f9cd541a8f5a64ab97) )
	206	ROM_LOAD( "4134_1024k.bin", 0x000000, 0x100000, CRC(49d8055a) SHA1(d46cef771a63dc8024fe36d7ab5b959087ac999f) )
	207	ROM_LOAD( "4817_1024k.bin", 0x000000, 0x100000, CRC(3f30863a) SHA1(dc955bd4d3ca71e01214a49e5d0aba615270c03c) )
	208	ROM_LOAD( "5101_256k.bin", 0x000000, 0x040000, CRC(e8a9224e) SHA1(5108e1025f48071c07a6823661d708c66dee97a9) )
	209	ROM_LOAD( "5838_256k.bin", 0x000000, 0x040000, CRC(5be2413d) SHA1(b9489e883c650b5e5fe2f83a32237dbf74f0e9f1) )
210	210	ROM_END
211	211	// See src/emu/gamedrv.h for details
212	212	// For a game:

trunk/src/mess/layout/tb303.lay
r248551	r248552
15	15	<bounds left="0" right="100" top="0" bottom="100" />
16	16
17	17	<!-- 21 LEDs: D201-D221 -->
18
	18
19	19	<bezel name="x.0" element="led"><bounds x="1" y="10" width="1" height="1" /></bezel> <!-- d201 -->
20	20
21	21	<bezel name="x.0" element="led"><bounds x="10" y="2" width="1" height="1" /></bezel> <!-- d202 -->

trunk/src/mess/machine/amstrad.c
r248551	r248552
2098	2098	if(m_system_type != SYSTEM_GX4000)
2099	2099	{
2100	2100	if(m_fdc) // if FDC is present (it isn't on a 464)
2101		{
	2101	{
2102	2102	if ((offset & (1<<7)) == 0)
2103	2103	{
2104	2104	unsigned int b8b0 = ((offset & 0x0100) >> (8 - 1)) \| (offset & 0x01);

trunk/src/tools/nltool.c
r248551	r248552
273	273
274	274	input_t()
275	275	{
276
277	276	}
278	277	input_t(netlist::netlist_t *netlist, const pstring &line)
279	278	{

trunk/src/tools/nlwav.c
r248551	r248552
90	90	private:
91	91	struct riff_chunk_t
92	92	{
93		char group_id[4];
94		unsigned filelen;
95		char rifftype[4];
	93	char group_id[4];
	94	unsigned filelen;
	95	char rifftype[4];
96	96	};
97	97
98	98	struct riff_format_t
99	99	{
100		char signature[4];
101		unsigned fmt_length;
102		short format_tag;
103		short channels;
104		unsigned sample_rate;
105		unsigned bytes_per_second;
106		short block_align;
107		short bits_sample;
	100	char signature[4];
	101	unsigned fmt_length;
	102	short format_tag;
	103	short channels;
	104	unsigned sample_rate;
	105	unsigned bytes_per_second;
	106	short block_align;
	107	short bits_sample;
108	108	};
109	109
110	110	struct riff_data_t
111	111	{
112		char signature[4];
113		unsigned len;
	112	char signature[4];
	113	unsigned len;
114	114	// data follows
115	115	};
116	116
r248551	r248552
144	144
145	145	void convert(nlwav_options_t &opts)
146	146	{
147
148	147	wav_t wo(opts.opt_out(), 48000);
149
	148
150	149	FILE *FIN = std::fopen(opts.opt_inp(),"r");
151	150	if (FIN==NULL)
152	151	throw netlist::fatalerror_e("Error opening input file: %s", opts.opt_inp().cstr());
153
	152
154	153	double dt = 1.0 / (double) wo.sample_rate();
155	154	double ct = dt;
156	155	//double mean = 2.4;
r248551	r248552
165	164	int n = 0;
166	165	//short sample = 0;
167	166
168
	167
169	168	while(!std::feof(FIN))
170	169	{
171	170	#if 1
r248551	r248552
212	211	v = 32000.0;
213	212	else if (v<-32000.0)
214	213	v = -32000.0;
215		sample = v;
	214	sample = v;
216	215	//printf("%f %f\n", t, v);
217	216	#endif
218	217	}
r248551	r248552
270	269	}
271	270
272	271	/*
273		Der Daten-Abschnitt enthält die Abtastwerte:
274		Offset Länge Inhalt Beschreibung
275		36 (0x24) 4 'data' Header-Signatur
276		40 (0x28) 4 <length> Länge des Datenblocks, max. <Dateigröße> − 44
	272	Der Daten-Abschnitt enth??lt die Abtastwerte:
	273	Offset L??nge Inhalt Beschreibung
	274	36 (0x24) 4 'data' Header-Signatur
	275	40 (0x28) 4 <length> L??nge des Datenblocks, max. <Dateigr????e>?????????44
277	276
278		0 (0x00) char 4 'RIFF'
279		4 (0x04) unsigned 4 <Dateigröße> − 8
280		8 (0x08) char 4 'WAVE'
	277	0 (0x00) char 4 'RIFF'
	278	4 (0x04) unsigned 4 <Dateigr????e>?????????8
	279	8 (0x08) char 4 'WAVE'
281	280
282	281	Der fmt-Abschnitt (24 Byte) beschreibt das Format der einzelnen Abtastwerte:
283		Offset Länge Inhalt Beschreibung
284		12 (0x0C) 4 'fmt ' Header-Signatur (folgendes Leerzeichen beachten)
285		16 (0x10) 4 <fmt length> Länge des restlichen fmt-Headers (16 Bytes)
286		20 (0x14) 2 <format tag> Datenformat der Abtastwerte (siehe separate Tabelle weiter unten)
287		22 (0x16) 2 <channels> Anzahl der Kanäle: 1 = mono, 2 = stereo; mittlerweile sind auch mehr als 2 Kanäle (z. B. für Raumklang) möglich.[2]
288		24 (0x18) 4 <sample rate> Samples pro Sekunde je Kanal (z. B. 44100)
289		28 (0x1C) 4 <bytes/second> Abtastrate · Frame-Größe
290		32 (0x20) 2 <block align> Frame-Größe = <Anzahl der Kanäle> · ((<Bits/Sample (eines Kanals)> + 7) / 8) (Division ohne Rest)
291		34 (0x22) 2 <bits/sample> Anzahl der Datenbits pro Samplewert je Kanal (z. B. 12)
	282	Offset L??nge Inhalt Beschreibung
	283	12 (0x0C) 4 'fmt ' Header-Signatur (folgendes Leerzeichen beachten)
	284	16 (0x10) 4 <fmt length> L??nge des restlichen fmt-Headers (16 Bytes)
	285	20 (0x14) 2 <format tag> Datenformat der Abtastwerte (siehe separate Tabelle weiter unten)
	286	22 (0x16) 2 <channels> Anzahl der Kan??le: 1 = mono, 2 = stereo; mittlerweile sind auch mehr als 2 Kan??le (z. B. f??r Raumklang) m??glich.[2]
	287	24 (0x18) 4 <sample rate> Samples pro Sekunde je Kanal (z. B. 44100)
	288	28 (0x1C) 4 <bytes/second> Abtastrate????????Frame-Gr????e
	289	32 (0x20) 2 <block align> Frame-Gr????e = <Anzahl der Kan??le>????????((<Bits/Sample (eines Kanals)>???+???7)???/???8) (Division ohne Rest)
	290	34 (0x22) 2 <bits/sample> Anzahl der Datenbits pro Samplewert je Kanal (z. B. 12)
292	291	*/

trunk/src/version.c
r248551	r248552
8	8
9	9	***************************************************************************/
10	10
11		#define BARE_BUILD_VERSION "0.163"
	11	#define BARE_BUILD_VERSION "0.164"
12	12
13	13	extern const char bare_build_version[];
14	14	extern const char build_version[];

https://github.com/mamedev/mame/commit/1b452e3bfb48e9c77e705a60ab285c382d457e8a

199869 Revisions